12-20-2013 07:08 AM
I am trying to two decimated clocks out of one clock coming from the mmcm so that I totally have 3 clocks in the system.
My application needs this.
First I tried to put a BUFGCE on the BUFG on the clock and the vivado drc check didn't allow it. This is series 7 part.
I understand that one possible way to do this is use BUFHCE on the BUFG and use the clock enable on the BUFHCE to control the clock.
But I now have a problem. From the documentation BUFHCE is limited to only one clock region?
My consuming IPs for the two clocks can be spread across multiple regions.
My options are:
1. Can I create just two of the clocks using 2 BUFHCEs from the main clock and assume vivado will replicate the BUFHCE as needed
2. Should I instead insert enough BUFHCEs and make sure that the loads on each will be well within a clock region capacity.
3. Is there any attribute like max fanout on BUFHCE which will make the tool do this for me?
12-20-2013 09:50 AM - edited 12-20-2013 09:51 AM
I presume you want these three clocks to be phase aligned so that you can cross synchronously between the 3 domains? To do this, all three clocks have the same types of clocking resources on all paths.
There are two ways to do this.
The reality is that every global domain (generated by a BUFG) goes through exactly one BUFH on its way to fabric logic. If you use the BUFG "directly" the tool infers the proper BUFHs at the time that it maps the logic resources to clock regions. Because of this, if you use a BUFHCE after a BUFG, then the manually instantiated BUFHCE is used instead of the automatically inserted BUFH, and hence the outputs of the clocks are balanced. But, as you mentioned, this restricts logic on the BUFHCE domain to one clock region (each). You can always manually partition the design and use multiple BUFHCEs with the same CE, but that is very cumbersome...
The other choice is to use BUFGCEs. But, you cannot (or should not) cascade BUFGs with BUFGCEs - these are the same resources.
So, what you should do is take the clock out of your MMCM output (say the CLKOUT0 output) and feed it directly to the .I input of three clock buffers; one BUFG, and two BUFGCEs (and drive the CE of the BUFGCEs as you need). Since each of the clocks goes through exactly one BUFGCTRL (which is the cell that is actually used to implement both a BUFG and a BUFGCE, as well as the BUFGMUX), the three clocks will be in phase.
12-20-2013 10:00 AM
If course, there is always the other solution - clock them all on the BUFG. For the FFs on the two decimated "domains" simply use the CE of the flip-flops...
12-20-2013 09:30 PM
Hi Avrum, This is perfect! One question is whether the mmcm compensation will still be effectively like it is for one clock? Or will it get confused seeing 3 buf* elements.
12-22-2013 08:51 AM