02-02-2010 11:07 PM
On a practical note: you have to fake this. To emulate a NxM bit 2-D port, use a vector of NxM. You can have the convenience of a 2-D array inside your module if you provide a conversion from the 1-D port to the 2-D easy representation. Waveform debugging of inter-module signals is of course a bit tedious.
AFAIK, SystemVerilog does allow 2-D ports but the Xilinx tools don't support that yet. It would probably be rather trivial to add this as it is supported for VHDL.