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fpga_freak
Observer
Observer
3,428 Views
Registered: ‎11-01-2007

Declaring 2 D Ports in Verilog

Hi,

 

  Anyone know, how to declare a 2-D port in Verilog.

 

regards,

freak

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2 Replies
ywu
Xilinx Employee
Xilinx Employee
3,416 Views
Registered: ‎11-28-2007

Verilog doesn't allow 2 dimensional ports.
Cheers,
Jim
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woutersj
Explorer
Explorer
3,401 Views
Registered: ‎07-27-2009

Hi,

 

On a practical note: you have to fake this. To emulate a NxM bit 2-D port, use a vector of NxM. You can have the convenience of a 2-D array inside your module if you provide a conversion from the 1-D port to the 2-D easy representation. Waveform debugging of inter-module signals is of course a bit tedious.

 

AFAIK, SystemVerilog does allow 2-D ports but the Xilinx tools don't support that yet. It would probably be rather trivial to add this as it is supported for VHDL.

 

Cheers,

Johan

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