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Adventurer
Adventurer
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Registered: ‎09-21-2016

Delay between input clock and MMCM output clock

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Hi everyone,

I give 50 Mhz input to the clock wizard and use MMCM scheme to generate 80 MHz scheme. In the simulation I saw there is a delay between input clock and generated clock. What is this delay for? Is there any way I can control this delay?

 

12.jpg

Any suggestion will be very helpful.

 

Thank you

Rappy saha

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Guide
Guide
5,393 Views
Registered: ‎01-23-2009

When you say "delay" between the clocks, you don't mean a phase delay, but a delay between the time the input clock starts running and the output clock becomes valid... (at least that is what I see from your timing diagram).

 

This is modelling the real behavior of the MMCM. The MMCM is a PLL based clock generation block that takes time to lock to the incoming clock. The maximum time required for the lock is specified in the datasheet - for example for a Kintex-7 it is in DS189, Table 37, MMCM_Tlockmax, which is specified as 100us. In your simulation you are seeing only 10us; the simulation model does not model the full 100us since that wastes simulation time...

 

But the up to 100us is real and you need to account for it in your system design. The MMCM will issue the LOCKED output when lock is achieved; it is customary to use the !LOCKED output of the MMCM as an input to the reset generation mechanism for the logic that is running on the of the MMCM output clocks.

 

Avrum

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Highlighted
Guide
Guide
5,394 Views
Registered: ‎01-23-2009

When you say "delay" between the clocks, you don't mean a phase delay, but a delay between the time the input clock starts running and the output clock becomes valid... (at least that is what I see from your timing diagram).

 

This is modelling the real behavior of the MMCM. The MMCM is a PLL based clock generation block that takes time to lock to the incoming clock. The maximum time required for the lock is specified in the datasheet - for example for a Kintex-7 it is in DS189, Table 37, MMCM_Tlockmax, which is specified as 100us. In your simulation you are seeing only 10us; the simulation model does not model the full 100us since that wastes simulation time...

 

But the up to 100us is real and you need to account for it in your system design. The MMCM will issue the LOCKED output when lock is achieved; it is customary to use the !LOCKED output of the MMCM as an input to the reset generation mechanism for the logic that is running on the of the MMCM output clocks.

 

Avrum

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Adventurer
Adventurer
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Registered: ‎09-21-2016

Hi @avrumw,

Thanks for your reply.

 

Yeah you are right. The time between input clock locked and output clock locked is different in practical than simulation. Although, for kintex-7 (-2 speed grade) it is maximum 100 us , this time is random i.e. I actually don't know how to control this time. I just can measure to know what is the time actually.

The lock time difference between input and output clock:

19.jpg

The lock signal indicate when the clk_out port can out clock signal. Besides, for my case, I am using two clock wizard the output clock of the first wizard is the input of the second clock wizard. That's why I have two lock signal. For the MMCM phase shifting, all phase increment/decrement have to be done before the lock signal goes high for the output signal. 

 

Thanks

Rappy

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