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Registered: ‎02-27-2018

Deserializing high speed bitstream

Hello,

 

I am trying deserialize data that come out of a LM98640 into 14 bits words:

Attached you can find a figure of the signals out of the LM98640.

I need to deserialize the signals TXOUT1 and TXOUT2:

A differential clock (TXCLK) is also output with transitions aligned with the center of the data eye. Data rates
range from 80Mbps up to 640 Mbps.

(TXOUT1 and TXOUT2 changes as fast as a 640 MHz clock)

What kind of FPGA should i use to work at these rates?

Can i use flip flops to capture the data and a 14 bit wide shift register to pack this into words of 14 bits wide?

Or is it more complex at these rates? Am i going to face metastability problems since i assume a will be facing crossing time domains between the clock sampling the DATA out of the LM98640 and the clock of the FPGA.

The data deserialized is going to be provided to a NI DAQ or stored in a RAM.

What kind of xilinx FPGA should i use?

 

Thank you for your help

 

 

figure.png
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Scholar
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Registered: ‎08-07-2014

Re: Deserializing high speed bitstream

@lebowski,

 

What kind of FPGA should i use to work at these rates?

I see that your txclk is really a high speed clk here.

Look for higher speed grade 7 series FPGAs.

 

Can i use flip flops to capture the data and a 14 bit wide shift register to pack this into words of 14 bits wide?

It is no doubt DDR signal, with the data changing when txclk is stable.

So you must use an IDDR primitive directly for ch1 data and ch2 data. Check out 7series Library Guide for more info on IDDRs.

 

I would also check out the Fmax values for the clock buffers and IDDRs for the FPGA chosen.

 

Or is it more complex at these rates?

Sure it would be at 640MHz.

 

 

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Registered: ‎06-21-2017

Re: Deserializing high speed bitstream

Since the max data rate is 640 Mbps and this is a DDR interface, isn't the clock speed 320 MHz?  I agree that the best choice is a fast 7 series.  The biggest issue that I see is the discontinuous nature of the clock.  You can't run  a shift register on both edges of the clock, you really need two shift registers, one on the rising edge, one on the falling edge.  I glanced at the data sheet for that part.  Makes you wonder what those guys were thinking.

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Registered: ‎08-07-2014

Re: Deserializing high speed bitstream

Since the max data rate is 640 Mbps and this is a DDR interface, isn't the clock speed 320 MHz? 

I agree.

 

The biggest issue that I see is the discontinuous nature of the clock. 

I think the clk is continuous (speculating), someone was a bit lazy while creating a technically perfect drawing. ;-)

 

Seems like the OP has not visited here for sometime!

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Registered: ‎03-31-2016

Re: Deserializing high speed bitstream

Start of by reading XAPP524 on interfacing serial LVDS ADCs with FPGAs.

 

You will basically use the ISERDES components of the FPGA driven by the TXCLK coming out of your LM device.  Depending on what you intend to do with the data a Kintex 7 or maybe even an Artix 7 should work.  You will need to check the AC specifications for the ISERDES to figure out which speed grade you need.

 

Since it is not an embedded clock protocol and your speeds can go so low you cannot use the transceivers.  

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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

Yes in fact the TXCLK is 320 MHz at its maximum.

I have been reading xapp524 and i understand that i need to realign my TXCLK with data's transition.

I am not sure that i understood that right actually (therfore the use of IDELAYE2 ?)

Is it going to be a problem if TXCLK stays at '0' between two words?

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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

Unfortunatly the clk is not continuous, it stays at zero between each word sent, does this complicate the issue that much? i'm going to use the ISERDESE2 for the deserialization
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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

I have another signal INCLK, it's frequency is 8 times lower than the frequency of the data.

INCLK is continuous, maybe i could use an MMCM to match the frequency of the data and then i will have to delay it to align its transitions with the data transitions.

But i don't know if it is possible to multiply a frequency and then delay the signal before entering in the CLK and CLKDIV of the ISERDESE2?

dual_lane_quad_lane.png
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Registered: ‎08-07-2014

Re: Deserializing high speed bitstream

@lebowski,

 

I have another signal INCLK, it's frequency is 8 times lower than the frequency of the data.

INCLK is continuous, maybe i could use an MMCM to match the frequency of the data and then i will have to delay it to align its transitions with the data transitions.

No, don't make it so complicated and I think it would be incorrect.

 

Use the discontinuous TXCLK.

You have the marker signal TXFRM, when this signal is going HIGH you have data coming in. After this you know that only 7 bits are received. So you know when to start and stop with sampling with your data.

 

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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

So does this mean i should just use TXCLK for CLK in the ISERDESE2 and TXFRM for CLKDIV?

I thought that CLK and CLKDIV must be phase aligned in order for the ISERDESE2 to work correctly.

I don't really understand how the ISERDESE2 uses the signal CLKDIV

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Registered: ‎08-07-2014

Re: Deserializing high speed bitstream

Yes TXCLK for CLK in the ISERDESE2 for sure.

 

See this post: https://forums.xilinx.com/t5/Simulation-and-Verification/ISERDES-and-DDR-input/td-p/695952

 

 

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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

Since my TXCLK is not continuous can i still use it through a BUFR to divide its frequency and construct a phase aligned CLKDIV?

 

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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

I tried to create a phase aligned clkdiv using my discontinuous txclk through a BUFR but the output is a signal that doesn't have a constant frequency, therefore i don't see another solution but using the INCLK signal passing it through a MMCM to multiply it's frequency and then delaying the data

BUFR.png
dual_lane_quad_lane.png
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Re: Deserializing high speed bitstream

So finally i have advanced on the problem that i have:

Out of the ADC i have for 4 main signals:

The INCLK (the frequency of INCLK is 8 time lower than the frequency of TXCLK, they are not phase aligned)

The TXCLK (This clocks transition is aligned with the center of the data eye TXOUT, TXCLK is a discontinuous clock)

The TXFRM (This signal has its edges aligned with edges of TXOUT)

and the TXOUT the data signal.

To deserialize correctly using an ISERDESE2 i need to have;

1) CLK and CLKDIV phase aligned with CLK transitions centered with the center of the data eye

2) I need to respect the clocking arrangement for the networking mode

2.1) CLK driven by BUFIO and CLKDIV driven by BUFR

2.2) CLK driven by MMCM or PLL and CLKDIV driven by CLKOUT[0:6] of same MMCM or PLL.

So basically there were two different strategies to achieve this

First one was to use TXCLK as CLK for the sampling and to respect the clock arrangement i need to generate CLKDIV by passing TXCLK through a BUFR, but since TXCLK is a discontinuous clock the output of the BUFR is a signal with a frequency which is not constant and i cannot use as a CLKDIV.

The second strategy was to use the INCLK pass through a MMCM to mutliply it's frequency by 8: INCLK and INCLK*8 (output of the MMCM) are phase aligned so i can use them as CLK and CLKDIV. but the problem is that the transition of (INCLK*8 = CLK) are not aligned on the center of the data eye. To achieve that i need to delay the data signal looking at the data sheet by at least 7000 ps (tDOD + tQSR) (on the figure attached for quad lane mode) whereas with IDELAYE2 component the maximum delay is 32 taps * 78 ps =2496 ps.

So finally none of the strategies work.

Does anyone has an idea?

Thank you for your help

 

 

dual_lane_quad_lane.png
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Registered: ‎06-21-2017

Re: Deserializing high speed bitstream

Bring TxCLK into a local clock buffer.  Use it to register your input data and to clock 4 shift registers, either the four data streams from the quad lane, or two rising edge and two falling edge shift registers from the dual lane.  Clock data from the shift registers into a FIFO when you detect a rising edge on the TxFRM signal.  You will need to interweave the data from the shift registers at the input to the FIFO.  You can read from the FIFO on your system clock whenever you have data in it.  I think this will work with a 7 series device.

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Registered: ‎02-27-2018

Re: Deserializing high speed bitstream

Okay thank you, so no more ISERDESE2?

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