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logan28
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Registered: ‎01-08-2010

Design with gated external clock

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Hi, I'm sort of new to FPGA. I was wondering if I can have a design where the external clock to my FPGA be on and off periodicly. I know Xilinx FPGA uses a Digital Clock Manager (DCM) and nees to phase lock (or delay lock using flip flops). So my design (FPGA) will have external clock that sometimes are turn off when the FPGA is not needed, is this a practical design or this is usually not recommended since the DCM requires some time to lock.

 

But what if I don't use DCM in my design, can the incoming clock be turn of and on then... will logic recover from previous stop state?

 

Thanks in advance for any advice.

 

Note: My design that I'm looking into is a pretty simple design where FPGA control about 200 switches based on the command it received. It will probably run at 40 MHz.

 

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gszakacs
Professor
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Registered: ‎08-14-2007

You don't have to use the DCM.  The logic inside the FPGA is completely static, so

there should be no problem stopping the clock as long as you want the FPGA to

do absolutely nothing while the clock is stopped.  Data setup/hold time windows

are a bit better when using a DCM, but at 40 MHz you should have no problem

using a clock without a DCM.  Make sure your clock goes to a global clock input

or "GC" (global clock capable) pin as it is called in the newer parts.  These pins

have a very short dedicated route to a global clock buffer.  Delays built into the

I/O flip-flops (between the pin and the D input) ensure you don't have a

positive hold time requirement.   For your application I would select the part

based on your I/O requirements only.  Almost any part should be adequate to meet

the timing and hold your design size.  You may find that your pin requirements

force you to use a part that is significantly larger than you need.  In that case

you might consider breaking the design into two smaller parts to save money.

 

HTH,

Gabor

-- Gabor

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gszakacs
Professor
Professor
4,776 Views
Registered: ‎08-14-2007

You don't have to use the DCM.  The logic inside the FPGA is completely static, so

there should be no problem stopping the clock as long as you want the FPGA to

do absolutely nothing while the clock is stopped.  Data setup/hold time windows

are a bit better when using a DCM, but at 40 MHz you should have no problem

using a clock without a DCM.  Make sure your clock goes to a global clock input

or "GC" (global clock capable) pin as it is called in the newer parts.  These pins

have a very short dedicated route to a global clock buffer.  Delays built into the

I/O flip-flops (between the pin and the D input) ensure you don't have a

positive hold time requirement.   For your application I would select the part

based on your I/O requirements only.  Almost any part should be adequate to meet

the timing and hold your design size.  You may find that your pin requirements

force you to use a part that is significantly larger than you need.  In that case

you might consider breaking the design into two smaller parts to save money.

 

HTH,

Gabor

-- Gabor

View solution in original post

logan28
Visitor
Visitor
3,831 Views
Registered: ‎01-08-2010

Thanks for the reply, I'm moving forward with your recommendation.. but since I'm on the topic of clock; I was wondering if anyone knows that if I need a clock to configure the FPGA. I chose the Xilinx Spartan 3AN since it has internal Flash for FPGA configuration (no external PROM needed to hold configuration), will I need to provide a clock during the power on sequence to configure the Spartan 3AN FPGA?

 

 

 

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gszakacs
Professor
Professor
3,827 Views
Registered: ‎08-14-2007

All Xilinx FPGA's have internal clock oscillators specifically for configuration.  For

parts with external configuration PROM, this would be driven on the CCLK pin.

For the Spartan 3AN, the clock would be internal to the package during self-

config from the embedded flash, but I believe it can also be programmed from

an external PROM like other Spartan 3A parts.  In any case you don't need

any on-board clock for the "master" configuration modes, or for loading

the FPGA or embedded flash via JTAG.

-- Gabor
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