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Explorer
Explorer
10,011 Views
Registered: ‎05-31-2015

Dual port BRAM read unsuccessful from custom vhdl module

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Hi,

 

 I am implementing a shared memory. I am using axi dual port BRAM from XPS .port A is connected to microblaze and port B to my vhdl module that reads and write signals. I can read and write well from microblaze. But I can write successfully from vhdl code and when I tried to read a location it fails.It simply shows the data wrote previously, but I am trying to read from a different location that has different data. Any suggestions??w1.PNG

 

 

These are the connections in xps.Below given is my vhdl code :

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

 

entity bramblock is

   port

   (

     RESET : IN std_logic;

                                FT2232_UART_SIN : IN std_logic;

                                CLK_100MHZ : IN std_logic;

                                axi_spi_0_SPISEL_pin : IN std_logic;

                                --axi_bram_ctrl_0_bram_block_1_BRAM_Rst_B_pin : IN std_logic;

                                --axi_bram_ctrl_0_bram_block_1_BRAM_Clk_B_pin : IN std_logic;

                                ---axi_bram_ctrl_0_bram_block_1_BRAM_EN_B_pin : IN std_logic;

                                --axi_bram_ctrl_0_bram_block_1_BRAM_WEN_B_pin : IN std_logic_vector(0 to 3);

                                --axi_bram_ctrl_0_bram_block_1_BRAM_Addr_B_pin : IN std_logic_vector(0 to 31);

                                --axi_bram_ctrl_0_bram_block_1_BRAM_Dout_B_pin : IN std_logic_vector(0 to 31);   

                                rzq : INOUT std_logic;

                                mcbx_dram_udqs : INOUT std_logic;

                                mcbx_dram_dqs : INOUT std_logic;

                                mcbx_dram_dq : INOUT std_logic_vector(15 downto 0);

                                axi_spi_0_SCK_pin : INOUT std_logic;

                                axi_spi_0_MISO_pin : INOUT std_logic;

                                axi_spi_0_MOSI_pin : INOUT std_logic;

                                axi_spi_0_SS_pin : INOUT std_logic;     

                                mcbx_dram_we_n : OUT std_logic;

                                mcbx_dram_udm : OUT std_logic;

                                mcbx_dram_ras_n : OUT std_logic;

                                mcbx_dram_ldm : OUT std_logic;

                                mcbx_dram_clk_n : OUT std_logic;

                                mcbx_dram_clk : OUT std_logic;

                                mcbx_dram_cke : OUT std_logic;

                                mcbx_dram_cas_n : OUT std_logic;

                                mcbx_dram_ba : OUT std_logic_vector(1 downto 0);

                                mcbx_dram_addr : OUT std_logic_vector(12 downto 0);

                                GPIO_HEADER_P2_PORT0 : OUT std_logic_vector(31 downto 0);

                                FT2232_UART_SOUT : OUT std_logic;

                                --axi_bram_ctrl_0_bram_block_1_BRAM_Din_B_pin : OUT std_logic_vector(0 to 31);

 

      d : in std_logic;

 

      q : out std_logic;

                               

                                chk: out std_logic

   );

end entity bramblock;

 

architecture Behavioral of bramblock is

signal add1:std_logic_vector(0 to 31) :=(others=>'0');

signal we1: std_logic_vector(0 to 3):=(others=>'0');

signal en1:std_logic:='0';

signal cnt:std_logic:='0';

signal dout1 :  std_logic_vector(0 to 31):=(others=>'0');

signal din1 :  std_logic_vector(0 to 31):=(others=>'0');

signal start:  std_logic_vector(31 downto 0) :=(others=>'0');

COMPONENT system

                PORT(

                                RESET : IN std_logic;

                                FT2232_UART_SIN : IN std_logic;

                                CLK_100MHZ : IN std_logic;

                                axi_spi_0_SPISEL_pin : IN std_logic;

                                axi_bram_ctrl_0_bram_block_1_BRAM_Rst_B_pin : IN std_logic;

                                axi_bram_ctrl_0_bram_block_1_BRAM_Clk_B_pin : IN std_logic;

                                axi_bram_ctrl_0_bram_block_1_BRAM_EN_B_pin : IN std_logic;

                                axi_bram_ctrl_0_bram_block_1_BRAM_WEN_B_pin : IN std_logic_vector(0 to 3);

                                axi_bram_ctrl_0_bram_block_1_BRAM_Addr_B_pin : IN std_logic_vector(0 to 31);

                                axi_bram_ctrl_0_bram_block_1_BRAM_Dout_B_pin : IN std_logic_vector(0 to 31);   

                                rzq : INOUT std_logic;

                                mcbx_dram_udqs : INOUT std_logic;

                                mcbx_dram_dqs : INOUT std_logic;

                                mcbx_dram_dq : INOUT std_logic_vector(15 downto 0);

                                axi_spi_0_SCK_pin : INOUT std_logic;

                                axi_spi_0_MISO_pin : INOUT std_logic;

                                axi_spi_0_MOSI_pin : INOUT std_logic;

                                axi_spi_0_SS_pin : INOUT std_logic;     

                                mcbx_dram_we_n : OUT std_logic;

                                mcbx_dram_udm : OUT std_logic;

                                mcbx_dram_ras_n : OUT std_logic;

                                mcbx_dram_ldm : OUT std_logic;

                                mcbx_dram_clk_n : OUT std_logic;

                                mcbx_dram_clk : OUT std_logic;

                                mcbx_dram_cke : OUT std_logic;

                                mcbx_dram_cas_n : OUT std_logic;

                                mcbx_dram_ba : OUT std_logic_vector(1 downto 0);

                                mcbx_dram_addr : OUT std_logic_vector(12 downto 0);

                                GPIO_HEADER_P2_PORT0 : OUT std_logic_vector(31 downto 0);

                                FT2232_UART_SOUT : OUT std_logic;

                                axi_bram_ctrl_0_bram_block_1_BRAM_Din_B_pin : OUT std_logic_vector(0 to 31)

                                );

                END COMPONENT;

               

                attribute box_type : string;

                attribute box_type of system : component is "user_black_box";

               

               

begin

 

 

Inst_system: system PORT MAP(

                                RESET=>RESET,

                                FT2232_UART_SIN =>FT2232_UART_SIN ,

                                CLK_100MHZ =>CLK_100MHZ,

                                axi_spi_0_SPISEL_pin=>axi_spi_0_SPISEL_pin,

                                axi_bram_ctrl_0_bram_block_1_BRAM_Rst_B_pin =>'0' ,

                                axi_bram_ctrl_0_bram_block_1_BRAM_Clk_B_pin =>CLK_100MHZ,

                                axi_bram_ctrl_0_bram_block_1_BRAM_EN_B_pin =>en1,

                                axi_bram_ctrl_0_bram_block_1_BRAM_WEN_B_pin =>  we1,

                                axi_bram_ctrl_0_bram_block_1_BRAM_Addr_B_pin =>  add1,

                                axi_bram_ctrl_0_bram_block_1_BRAM_Dout_B_pin =>  dout1,

                                rzq =>    rzq,

                                mcbx_dram_udqs =>      mcbx_dram_udqs,

                                mcbx_dram_dqs =>mcbx_dram_dqs,

                                mcbx_dram_dq =>           mcbx_dram_dq ,

                                axi_spi_0_SCK_pin =>    axi_spi_0_SCK_pin,

                                axi_spi_0_MISO_pin=>axi_spi_0_MISO_pin,

                                axi_spi_0_MOSI_pin =>axi_spi_0_MOSI_pin,

                                axi_spi_0_SS_pin =>axi_spi_0_SS_pin,

                                mcbx_dram_we_n =>mcbx_dram_we_n,

                                mcbx_dram_udm =>       mcbx_dram_udm,

                                mcbx_dram_ras_n =>mcbx_dram_ras_n,

                                mcbx_dram_ldm =>mcbx_dram_ldm ,

                                mcbx_dram_clk_n =>mcbx_dram_clk_n,

                                mcbx_dram_clk =>mcbx_dram_clk,

                                mcbx_dram_cke =>mcbx_dram_cke,

                                mcbx_dram_cas_n =>mcbx_dram_cas_n ,

                                mcbx_dram_ba =>mcbx_dram_ba,

                                mcbx_dram_addr=>        mcbx_dram_addr,

                                GPIO_HEADER_P2_PORT0 =>start,

                                FT2232_UART_SOUT =>FT2232_UART_SOUT,

                                axi_bram_ctrl_0_bram_block_1_BRAM_Din_B_pin =>din1

                );

 

GPIO_HEADER_P2_PORT0<=start;            

 

 

 

process (CLK_100MHZ) is

   begin

      if rising_edge(CLK_100MHZ) then 

         if (RESET='0') then 

                                                                if(start(0)='1') then

                                                                                if(cnt='0') then

                                                                                                                add1<=(0=>'1',2=>'1',6=>'1',28=>'1',others=>'0');

                                                                                                                en1<='1';

                                                                                                                we1<=(others=>'1');

                                                                                                                dout1<=(29=>'1',31=>'1',others=>'0');

                                                                                                                cnt<='1';

 

                                                                                elsif (cnt=1)then

                                                                                                             add1<=(0=>'1',2=>'1',6=>'1',27=>'1',others=>'0');
                                                                                                             en1<='1';
                                                                                                                we1<=(others=>'0');
                                                                                                                dout1<=(others=>'0');
                                                                                                                cnt<=cnt+1;

                                                                                else

                                                                                                                                add1<=(others=>'0');

                                                                                                                                en1<='0';

                                                                                                                                we1<=(others=>'0');

                                                                                                                                dout1<=(others=>'0');

                                                                                                                                cnt<='1';

                                                end if;

                                                end if;

         end if;

      end if;

   end process;

 

 

chk<=start(0);   

end architecture Behavioral;

 

 

please make any suggestions.

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Accepted Solutions
Explorer
Explorer
18,862 Views
Registered: ‎05-31-2015

Re: Dual port BRAM read unsuccessful from custom vhdl module

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Hi,

 

I finally figured my error. You have to look for the value in read bus only after one more elsif (..) idle case since the value comes in bus with 1 clock time delay...

View solution in original post

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4 Replies
Xilinx Employee
Xilinx Employee
10,008 Views
Registered: ‎08-01-2008

Re: Dual port BRAM read unsuccessful from custom vhdl module

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check this documents
http://esca.korea.ac.kr/teaching/com509_CS/zynq/zedboard_xup/Vivado-based/ES-Design-Vivado-13.3/doc_source/lab3.pdf

http://www.uz.zgora.pl/~rwisniew/instrukcje/sw/sw_cw3.pdf
Thanks and Regards
Balkrishan
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Explorer
Explorer
9,996 Views
Registered: ‎05-31-2015

Re: Dual port BRAM read unsuccessful from custom vhdl module

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Hi,

 

 Thank you for replying, But those documents were based on how to add BRAM as peripheral. But I want to develop a shared memory on which you can operate from microblaze and vhdl code. I am facing difficulty in reading memory from vhdl. And need help in that.

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Explorer
Explorer
9,993 Views
Registered: ‎05-31-2015

Re: Dual port BRAM read unsuccessful from custom vhdl module

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Also in 'else' case in vhdl code cnt<=cnt....

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Explorer
Explorer
18,863 Views
Registered: ‎05-31-2015

Re: Dual port BRAM read unsuccessful from custom vhdl module

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Hi,

 

I finally figured my error. You have to look for the value in read bus only after one more elsif (..) idle case since the value comes in bus with 1 clock time delay...

View solution in original post

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