03-01-2011 11:35 PM
I have this machine learning circuit which I wish to implement on FPGA in such a way that when the circuit learns from the inputs, the FPGA can reconfigure itself (the learning part) dynamically at runtime.
This would involve dynamically regenerating the configuration bit stream at runtime when the circuit is learning. I have been searching around but couldn't find a relevant solution for it, as many of the dynamic reconfiguration methods were having the reconfiguration bit stream ready beforehand and load it at runtime. So is there a way I can do this on the fly?
03-02-2011 04:20 AM
03-02-2011 07:12 AM
you need some kind of BIT-File for Partial Reconfiguration. This files are e.g. generated by ISE.
In an FPGA,it's almost impossible to generate such a file. And btw. the filestructure is (1) not
documented and (2) device dependend.
One solution to your problem is, that the logic/data/settings for your algorithm resides in a BRAM.
Together with a simple reconfigurationlogic, you can update this content and restart your algorithm.
Simple Example: For a neuronal network, the adders/multipliers/topology etc. are "hardwired", while
the weights are stored in BRAMs. After several lerning steps, a simple logic feeds the ne weights
into the BRAMs.
03-02-2011 10:42 AM
You could always pre-generate partial using XAPP 290 and the differnced based flow in FPGA Editor. In this flow changes to the .ncd and be placed into a partial bit file that just has deviations from the prior design. Just be careful that the partial are played in the same order in which they are created.
07-14-2011 07:48 PM - edited 07-14-2011 08:21 PM
I would like to buy a development board for runtime reconfiguration self study.
What is the min. config. to do that?
Spartan-6 FPGA SP601 Evaluation Kit ?
Spartan-3A platform evaluation kit?
Please feel free to suggest.