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Teacher xilinxacct
Teacher
492 Views
Registered: ‎10-23-2018

Enhancement Idea: Using FPGA to speed up synthesis and implementation

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 Just curious…. Let’s say you have an Alveo or other high capability FPGAs… Couldn’t Xilinx utilize that horsepower to speed up the synthesis and implementation process? Using all those available gates to explore more paths, more optimization, etc...

 This would seem to be a motivation for users to ‘buy’ higher ends cards/dev kits, be a marketing differentiator, and reduce the wait time for users.

 If it were possible, I would certainly be interested in that offering.

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Scholar u4223374
Scholar
429 Views
Registered: ‎04-26-2015

Re: Enhancement Idea: Using FPGA to speed up synthesis and implementation

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It has been suggested several times, but there doesn't seem to be very much interest. Some of the tasks are inherently sequential and therefore not ideal for an FPGA, but I would have thought there were some things where feeding Vivado's C code to SDAccel would make sense.

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Scholar u4223374
Scholar
430 Views
Registered: ‎04-26-2015

Re: Enhancement Idea: Using FPGA to speed up synthesis and implementation

Jump to solution

It has been suggested several times, but there doesn't seem to be very much interest. Some of the tasks are inherently sequential and therefore not ideal for an FPGA, but I would have thought there were some things where feeding Vivado's C code to SDAccel would make sense.

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