FIFO IPcore: Fifo Primitive vs Block RAM implementation differences?
I was implementing a FIFO today and I was wondering what the difference between the FIFO Primitive and the Block RAM implementations are. From what I can understand, they use the same underlying RAM primitives, but the FIFO Primitive can't have different R/W aspects or dual clock domains.
Other than the obvious limitations which are outlined in the wizard, what are the other differences? What advantage does the FIFO Primitive give you over the Block RAM? For the record, I'm using 6-series Virtex, but this would apply to any family that has the FIFO Primitive I would think.
V6 includes some FIFO logic in the block ram of the FPGA. This should reduce the resources needed to implement a FIFO if it is already using a block ram and fits the capabilities of the FIFO primitive.
Although I have used the fifo primitive I have not taken the time to implement the same with a generic block ram fifo from coregen and compare the implementation resources, if you do so please post your results here :).