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santukms
Adventurer
Adventurer
4,554 Views
Registered: ‎09-15-2010

FIFO design...............

hi

one problem on fifo depth calculation..................

 

I am using the Endpoint for block plus and GTP RocketIO in my design, now i have data exchange between these two IP's. I need to have a FIFO. Please help me in this problem...

 

Here I have the application part of PCIe working at (62.5MHz or 125MHz clock) and we are getting 32bit of data per clock cycle.

means the data rate ia (62.5M*32=2Gbits/s=250Mbytes/s or 125M*32=4Gbits/s=500Mbytes/s)

 

But the clock rate of the GTP frame generator is (156.25MHz) and data rate is (156.25M*16=2.5Gbits/s=312.5Mbytes/s) in our design of GTP

 

now I need to have a fifo between the PCIe application and the GTP ROCKETIO. what depth of fifo is good?

 

will it be good to have a application clock runing at 62.5MHz or 125Mhz which is better for this application..........

Can we can have the GTP runing at the different clock speed will it be good ???

 

Please suggest me............

 

you know both PCIE and GTP continously runs..........which fifo design method can be best ,,,,,,,,,,,,,,,,,,,,,,

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5 Replies
gszakacs
Instructor
Instructor
4,550 Views
Registered: ‎08-14-2007

How many lanes is your PCIe interface?  This determines the actual data throughput rate,

not the internal clock speed at the user interface.  That clock only determines the peak

data rate.  If you're only using one (Gen 1) lane, then the average data rate cannot exceed 2.5 Gb/s

regardless of the internal clock speed.  In that case for 125 MHz user clock, the FIFO only needs to be as deep

as the maximum burst size at the user interface times (one minus the input data rate over the output data rate).

If you use the 62.5 MHz clock then the FIFO can have just a minimum depth assuming you will read

it whenever it is not empty.

 

-- Gabor

-- Gabor
santukms
Adventurer
Adventurer
4,546 Views
Registered: ‎09-15-2010

 

 

Thank you very much SIr for the reply........

 

I am using the x1 PCIe in ML506 Board....

 

Can you tell more about the Burst size? I don't know about that please....

In 62.5MHz clock design In case if fifo gets emptied we shouldn't read from fifo, right ......But the the GTP ROCKETIO will be running continuously right in that case should we reset the GTP,or just frame generator of the GTP or any other option you suggest me Sir

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mcgett
Xilinx Employee
Xilinx Employee
4,535 Views
Registered: ‎01-03-2008

If you have one interface running 125 MHz 32-bits wide and another running at 156.25 MHz 32-bits wide and the data stream has no idle times then you will always get data overruns or underuns depending on the transfer direction regardless of the size of the FIFO.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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santukms
Adventurer
Adventurer
4,532 Views
Registered: ‎09-15-2010

Hi   ,

Thank you very much for the reply....

 

In this case what  we can do the best?

any idea Sir.....

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eteam00
Professor
Professor
4,527 Views
Registered: ‎07-21-2009

What Ed (mcgett) is saying is:

You will get overruns or under-runs unless the data streams are perfectly matched in data bandwidth, if both interfaces must be transferring data constantly.

FIFOs do nothing more than smooth out the bursts in one interface feeding another interface.

 

A 100MB/sec port can work well with another port of "only" 80MB/sec, if the longterm average data transfer rate is 60MB/sec.  In this case, a FIFO would be useful for the brief 100MB/sec bursts between idle periods.  Without the FIFO, the 80MB/sec port would be over-run with the first data transfer burst from the 100MB/sec. port.

 

This is all stuff which you need to work out in your systems design.

 

-- Bob Elkind

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