05-05-2012 04:29 PM
Hello all, this seems like a good place to post our Digilent 2012 contest project for discussion. Our project is a 16-QAM communication system implementation on a Xilinx Spartan 3E board.
Here is a link to our final Youtube video:
Attached are the final report and presentation powerpoint slides. Your questions and comments are welcome. We will try our best to respond to any questions or comments you may have. Thanks.
05-07-2012 10:25 AM
Now all you need to do is actually send the carrier over hte air, receive the carrier, and then recover the symbol timing...
In a 16QAM microwave radio I built ages ago now, using a Xilinx 3042, we had receive five feedback loops: 1. Carrier recovery (the RF carrier), 2. symbol timing recovery, 3. AGC on the IF strip (maximize the sensitivity or the gain of the IF strip), 4 & 5 Center the DC levels for the I channel, and the Q channel (remove any offset).
And, to make thing more difficult, we also used sprea spectrum (the 16QAM was spread by a factor of 11 to meet FCC rules). The recovery of the spread signal was another feedback look, and the despreading (sync with spreading sequence) was another loop.
We called it the "hell of the 7 loops."
One had to recover the spread signal first (lock on carrier), despread next, find hte 16QAM symbol timing, etc. all the while adjusting the AGC to get all the bits in the right places (no overflow, enough signal)....
Not trying to distract from your accomplishments, but you have built the easy stuff. Now comesd the hard part.
05-07-2012 10:34 AM
Austin, you are every marketing department's worst nightmare! LMAO!
-- Bob Elkind
05-09-2012 06:03 AM
For students (with their limited time besides lectures) it's also remarkable that they acheived to build something functional mastering the big set of tools required for this. (Matlab-Sysgen-ISE).
What I'm missing in the project presentation is the synthesis /implementation result (e.g. excerpts from the .syr file).
Not only to get an idea of the ressource usage in the S3500E device, but now especially to compare the design result with some similar design that fitted into a (from todays point of view) tiny XC3042.
An interesting question here would be:
How much extra silicon must be spent/wasted when doing rapid prototyping with sysgen?
(Compared to a tailor-made design with XACT from the late 80s/early 90s.)
05-09-2012 06:36 AM
Way back in the 3042 day, we made the 1/2 raised square root cosine filters for transmit by using resistor summing ladders from IO pins (also implemented the D/A's for I and Q), and the receive ISM filters (the other half of the RSQRT) where analog LC filters. To have done all of these so long ago would nevr have fit those tiny parts!
05-09-2012 11:00 PM
thanks for the explanation.
I already wondered how you did it, expecting some special digital design tricks.
"Outsourcing" area consuming parts to some analog circuits sure helped a lot. :-)
Seeing it that way we can be grateful that todays FPGAs are capable of implementig the whole functionality of such designs.