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Visitor
Visitor
8,130 Views
Registered: ‎12-14-2013

FPGA stops, reprogramm: Impact Device IDCODE: 00001111111111111111111111111111

Hi guys,

 

I have a rather big design, which takes up to 90% of my Virtex 6 FPGA on the ML 605 development board. The design works flawlessy with small operating frequencies (50MHz), however if i try to increase the frequency up to 100 MHz (implementation succeeds, all timing constraints are met) my implemented design on the FPGA stops working. This could also indicate a problem with my design, however if I try to reprogramm the FPGA with impact I get the following message:

 

PROGRESS_START - Starting Operation.
INFO:iMPACT:583 - '2': The idcode read from the device does not match the idcode in the bsdl File.
INFO:iMPACT:1578 - '2':  Device IDCODE :        00001111111111111111111111111111
INFO:iMPACT:1579 - '2': Expected IDCODE:    00000100001001010000000010010011

 

The higher the frequency the faster the descibed behaviour occurs. At 50 MHz it never occurs, at 75MHz it once occured after several days, at 83 MHz several hours, at 100 MHz after up to one hour.

 

Does this mean the FPGA is about to stop working? Or could it be the implemented design? However as I said all timing constraints are met and there are no errors or serious warnings.

Unfortunately I don't have a second FPGA, which I could use for testing...

 

Best,

Paul

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Moderator
Moderator
8,126 Views
Registered: ‎02-16-2010

Your observations shows the JTAG circuit cannot work at frequencies more than 50MHz.

Check for any SI issues with TCK,TDI and TDO lines.
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Visitor
Visitor
8,120 Views
Registered: ‎12-14-2013

The frequency I was talking about is the internal clock frequency of my design.

I do not modify any other frequencies.

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Moderator
Moderator
8,113 Views
Registered: ‎02-16-2010

How are you changing the internal clock frequency?

The error message you have received is independent of the FPGA internal clock frequencies.

Check to see if there is any interference between TCK and your internal clock.

Still I would recommend to check for SI issues with TCK, TDI and TDO lines.
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Visitor
Visitor
8,104 Views
Registered: ‎12-14-2013

I use the 200 MHz PLL on the board to derive the clock for my design, yes this is independent of the this message. However the reported behaviour only occurs if I clock the design with higher frequencies.

 

What does SI stand for? How do I check for these issues?

 

However If i somehow program the device with a bitfile, which is not working, I should always be able to reprogram it, shouldn't I?

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Moderator
Moderator
8,096 Views
Registered: ‎02-16-2010

SI stands for Signal integrity. Probe the TCK, TDI and TDO using oscilloscope to compare in working and non working cases.

Check these lines in both cases,
1) while programming FPGA
2) When there is no programming operation

If there is any clock interference on the JTAG lines, then frequency of the failure will be more when the clock frequency is more.

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Visitor
Visitor
8,090 Views
Registered: ‎12-14-2013

Ok thank you, I will do so. I will report back, when I'm done.

 

One last point I want to mention: The device IDCode does not fail instantly after programming, this happens only after using the FPGA some time.

 

Thank you.

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Historian
Historian
8,070 Views
Registered: ‎02-25-2008


@venkata wrote:
Your observations shows the JTAG circuit cannot work at frequencies more than 50MHz.

Check for any SI issues with TCK,TDI and TDO lines.

You DO realize that he's using a Xilinx development board, right?

You DO realize that these problems occur when the design's clock frequency increases, not the JTAG clock, which can't run at more than 12 MHz from the USB Platform Cable 2 anyway.

----------------------------Yes, I do this for a living.
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Moderator
Moderator
8,062 Views
Registered: ‎02-16-2010

Sorry, It is my overlook at the first query that the issue happens on ML605 eval. board.

I do understand that the observation is with varying of design's clock frequency than the JTAG clock frequency.

But I do not understand how does the design's clock frequency could depend on the JTAG problem. The design's clock should only get generated after the bit file has been programmed.

How does this clock frequency will relate to the JTAG chain failure?

The issue could relate to design utilization...as an experiment a design with lower utilization can be tried at different clock frequencies..

Once the issue happens..pulse prog_b then try to initialize chain after few mins..check if the JTAG chain initialization is successful...

I am thinking about loading on the power supplies while the design is operating..

While doing this..monitor the supplies through system monitor in chipscope..

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Historian
Historian
8,051 Views
Registered: ‎02-25-2008


@masterp wrote:

 

One last point I want to mention: The device IDCode does not fail instantly after programming, this happens only after using the FPGA some time.


I don't think the FPGA on that board has a heat sink, but my guess is that when you run it for "awhile" at the higher frequencies, the die heats up enough to cause all sorts of problems.

 

I have an S6 design here that, withouth heatsinking, I can't reconfigure the FPGA after it runs for a short time.

 

Simple test: start cold. Configure the FPGA with the 100 MHz load. Let it run for awhile. Touch the top of the FPGA. If you burn your finger, it's too hot :)

----------------------------Yes, I do this for a living.
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Xilinx Employee
Xilinx Employee
6,374 Views
Registered: ‎01-03-2008

The most likely failure mechanism is that the power supply has shutdown due to a excessive current draw.  Are you seeing the Power Good LED (DS2) go off when this occurs?

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
6,362 Views
Registered: ‎12-14-2013


@bassman59 wrote:

@masterp wrote:

 

One last point I want to mention: The device IDCode does not fail instantly after programming, this happens only after using the FPGA some time.


 

Simple test: start cold. Configure the FPGA with the 100 MHz load. Let it run for awhile. Touch the top of the FPGA. If you burn your finger, it's too hot :)


 

There is an active cooler (radiator) on the FPGA. Temperatures reach up to 50 - 60 °C. That should be within the limits, shouldn't it?


@mcgett wrote:

The most likely failure mechanism is that the power supply has shutdown due to a excessive current draw.  Are you seeing the Power Good LED (DS2) go off when this occurs?


I did not so far, but I will take a closer look at it.

But it seems to be the opposite. A sudden drop of current seems to cause the problem. My design is completely pipelined (depth about 350), so almost all of the used slices are in use. All pipeline stages need an enable signal, which is forwarded to the next sage. If I unset the enable signal the whole design idles. This unsetting seems to cause the problem.

 

Should the board be capable to deal with such current draws and drops? Or is it my responsibility to avoid them?

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Xilinx Employee
Xilinx Employee
6,349 Views
Registered: ‎01-03-2008

> This unsetting seems to cause the problem.

 

If the design is suddenly going from 15A current draw on VCCINT to 1A current draw on VCCINT it may be causing a momentary spike voltage as the power supply continues to add charge that has nowhere to go and the higher voltage is triggering an overvoltage alarm.

 

In order to prevent damage to the FPGA, the over/under voltage settings on the Xilinx evaluation boards are set in a tight range.  It is possible to change the thresholds using a TI USB PMBUS module.

 

> Should the board be capable to deal with such current draws and drops?

 

While there is a significant amount of over design in the power supply system on the evaluation boards, covering all possible extreme cases would require more area, components and cost.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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Visitor
Visitor
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Registered: ‎12-14-2013

I removed the "feature" and I will test the current design over the weekend. I hope this solves the problem.

 

Is there another way to change thresholds, maybe even disable them without the TI USB PMBUS module? I only have a micro usb to usb cable (it's called xilinx platform usb cable, if I recall correctly) which I use for the JTAG to USB port on the board to program it.

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Xilinx Employee
Xilinx Employee
6,317 Views
Registered: ‎01-03-2008

> Is there another way to change thresholds,

 

No, this is the only way to change the programmed values in the power system.

------Have you tried typing your question into Google? If not you should before posting.
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Visitor
Visitor
6,302 Views
Registered: ‎12-14-2013

Even without current spikes or drops, the FPGA "crashes".

I ordered this TI module, I hope this fixes the problem.

 

However I'm really disappointed in Xilinx development boards... If I spend about 2000 $ for hardware I expect the hardware to work properly, especially if the bitfile generation succeeds without any errors or warnings, which would let me anticipate the problem...

 

 

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Xilinx Employee
Xilinx Employee
6,293 Views
Registered: ‎01-03-2008

Can you please explain what you mean by without current spikes or drops the FPGA crashes.

------Have you tried typing your question into Google? If not you should before posting.
Too many results? Try adding site:www.xilinx.com
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