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kevinkerliu
Visitor
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Registered: ‎02-04-2021

Hello,

I am looking to use an FPGA to generate pulses with nanosecond resolution, but I can't seem to find this spec. on the datasheets. Is anyone familiar with where I might be able to find this out?

Thank you!
Kevin

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drjohnsmith
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Teacher
911 Views
Registered: ‎07-09-2009

The problem at sub ns speeds 

   is not so much the FPGA as the board,

sub 1ns rise / fall times have multi GHz bandwidths,

    so you can not just use a standard multi pin header,

        your into the world of SMA or other special high speed connectors.

Also, driving the load, is like driving a capacitor,

    as the speed increases, the amount of current needed to get to a set voltage in the reduced time increases,

     thus higher speed outputs such as the GTX, found on some 7 series parts,

             are differential and around a 200 mV swing.

 

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drjohnsmith
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Registered: ‎07-09-2009

yes

 

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kevinkerliu
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Registered: ‎02-04-2021

where might that be?

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

So , we need to knwo a lot more abotu yo and what your doing then.

 

basic questions first

   what's your experience level in electronics, FPGAs and Xilinx

what OS on you computer, are you set up already for a particular Xilinx tool chain ?

What language do you expect to program the FPGA in ?

When yo say a ns pulse, is this a ns pulse that you can move around in time, and / or a pulse that you want that you want to vary the width of  ? if so what sort of resolution on varying the width are you lookgin for ?

Only then can we get down to asking what sort of thing are you wanting to do withthis ns pulse ? 

   is it driving off the FPGA or is it internal to the FPAG ,

       If off the FPGA , is it just on board or going off board ?

If off FPGA, what sort of load is this pulse meant  to be driving ? 

 

So yes, is still the answer, 

    but I'm afraid from the info so far that's about all we can say .

 

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kevinkerliu
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Registered: ‎02-04-2021

I would like to find a board for which the digital output cam resolve a 50ns pulse at a max pulse frequency of 100Hz with sharp transitions.

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drjohnsmith
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Teacher
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Registered: ‎07-09-2009

Any FPGA from Xilinx thats a 7 series will have at most a few ns rise / fall time, 

I am assuming this is an output of the FPGA ?

What voltage / format do you require ?

   what are you driving ?

 

 

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kevinkerliu
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Registered: ‎02-04-2021

Yes this is for an output of the FPGA as I'll be driving an ultrasonic pulse generator with digital inputs at 2.5/3.3 V.

Thank you again for all the help!

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kevinkerliu
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Registered: ‎02-04-2021

Another question... If I need the "sharp" transition to be < 1 ns of rise/fall time is there an Xilinx FPGA that could work?

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drjohnsmith
Teacher
Teacher
912 Views
Registered: ‎07-09-2009

The problem at sub ns speeds 

   is not so much the FPGA as the board,

sub 1ns rise / fall times have multi GHz bandwidths,

    so you can not just use a standard multi pin header,

        your into the world of SMA or other special high speed connectors.

Also, driving the load, is like driving a capacitor,

    as the speed increases, the amount of current needed to get to a set voltage in the reduced time increases,

     thus higher speed outputs such as the GTX, found on some 7 series parts,

             are differential and around a 200 mV swing.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>

View solution in original post

kevinkerliu
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890 Views
Registered: ‎02-04-2021

This was very informative, thank you!

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