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Explorer
Explorer
7,758 Views
Registered: ‎08-23-2011

Gated clock details - when a data pin (Q o/p of FF) is used as clock for next sync element? good or bad for FPGA?

hi,

 

from what i've read about clocks and fpgas, i guess gated clocks are bad for FPGA design (they tend to take the clock lines off the global clock tree and into the logic fabric leading to glitches etc and bad timing).

 

however how does the fabric react if we have a data pin being used as a clock pin for the next FF? such as that shown in the pic below -

Screenshot.png

 

This is a synthesis result - the Q output of the FDC is used as the G clock for the next element (LD). During synthesis, using synplify, this shows as gated clock (in the gated clock report section). So I was wondering if this type of clock (data used as clock) is good or bad for the overall FPGA design?

 

will this disimprove the timing? and if yes, is the only way around it by redesigning the logic?

 

please let me know ...

 

z.

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Historian
Historian
7,736 Views
Registered: ‎02-25-2008


@zubin_kumar31 wrote:

hi,

 

from what i've read about clocks and fpgas, i guess gated clocks are bad for FPGA design (they tend to take the clock lines off the global clock tree and into the logic fabric leading to glitches etc and bad timing).

 

however how does the fabric react if we have a data pin being used as a clock pin for the next FF? such as that shown in the pic below -


Depending on device family, the router will probably barf on this, because there are no routes from a logic output to a clock input on a flop. 

----------------------------Yes, I do this for a living.
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