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Anonymous
Not applicable
4,443 Views

General question on metastability

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Hi All,

 

Often in digital design, when we use RAM, counters, shift register, an Enable signal is used in a a similar fashion(RAM):

--

process(clk)
    begin
        if(rising_edge(clk)) then
            if(we = '1') then
                ram(addr) <= data;
            end if;

--

The question is, what happens if the rising edge of clock (clk) happens at the same time when "we" goes from low to high?  Is that  metastability( although in the same clock domain)?

Do I need as a designed to make sure "we" signal high occurs  before rising_edge of clock( setup time >0) or I am safe?

 

thank you

 

LT

 

 

 

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Instructor
Instructor
5,569 Views
Registered: ‎07-21-2009

In addition to Gabor's excellent comment:

 

In your example, the following signals must meet setup and hold timing requirements with respect to the clock positive edge:

  • we
  • addr
  • data

If the setup/hold time requirements are not respected, result (ram content/state) will be indeterminate.

 

Check the device datasheet for specific timing requirements.

 

-- Bob Elkind

SIGNATURE:
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Professor
Professor
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Registered: ‎08-14-2007

To avoid the possibility of metastability you need to meet setup and hold time to the

clock for the we signal.  Normally if we is also assigned in a clocked process, the

tools will take care of this for you.  In general it is a bad idea to use an asynchronous

signal to drive the we input of the RAM.

 

-- Gabor

-- Gabor
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Instructor
Instructor
5,570 Views
Registered: ‎07-21-2009

In addition to Gabor's excellent comment:

 

In your example, the following signals must meet setup and hold timing requirements with respect to the clock positive edge:

  • we
  • addr
  • data

If the setup/hold time requirements are not respected, result (ram content/state) will be indeterminate.

 

Check the device datasheet for specific timing requirements.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.

View solution in original post

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Anonymous
Not applicable
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Hi,

 

Meeting setup and hold times for "we" signal make sense. I thought that setup and hold times refer only to data with respect to clock relationship.

 

LT

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Instructor
Instructor
4,431 Views
Registered: ‎07-21-2009

Meeting setup and hold times for "we" signal make sense. I thought that setup and hold times refer only to data with respect to clock relationship.

 

And then there's address, of course.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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