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Observer yurivn
Observer
291 Views
Registered: ‎07-03-2018

General solution (step by step) for Warning: Number of Nodes with overlaps

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Hello everyone,

After reading many threads in forum about topic "Number of Nodes with overlaps" , I found some solutions for this case:

  • Change implementations strategy.
  • Optimize code to reduce resource.
  • Fix timing issue.
  • Change clock buffer.

But I don't know how to know exactly where "overlaps" from to choose the best solution.

So, my questions are:

  1. Is available a general solution for "overlaps" issue? (I hope receive an answer step by step)
  2. Anyone has another solution?

Let's share your experience to learn new things.

 

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Scholar u4223374
Scholar
252 Views
Registered: ‎04-26-2015

Re: General solution (step by step) for Warning: Number of Nodes with overlaps

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The general solution is "buy a bigger FPGA"...

The tools are complaining that, with the current layout on the FPGA, different sections of the design overlap (ie they occupy the same resources, which is not acceptable). This might be solvable by doing any of the things you mentioned:

- Changing implementation strategies might cause it to try a different layout that doesn't cause an overlap

- Reducing resource usage is obviously equivalent to buying a bigger FPGA; if there are fewer resources then each design section will be smaller and it'll be easier to place them without overlaps.

- Timing limitations determine where Vivado can place parts of the design. If you can loosen the limitations then Vivado has more flexibility in moving sections of the design so they won't overlap.

- Clock buffers are a concern because the clock infrastructure is coarsely-grained (at least in the 7-series chips, I don't know about UltraScale). Moving a clock buffer may cause Vivado to move a whole section of the design along with it.

 

However, after all of that, it's quite possible that the design simple doesn't fit on the chip you've selected.

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Scholar u4223374
Scholar
253 Views
Registered: ‎04-26-2015

Re: General solution (step by step) for Warning: Number of Nodes with overlaps

Jump to solution

The general solution is "buy a bigger FPGA"...

The tools are complaining that, with the current layout on the FPGA, different sections of the design overlap (ie they occupy the same resources, which is not acceptable). This might be solvable by doing any of the things you mentioned:

- Changing implementation strategies might cause it to try a different layout that doesn't cause an overlap

- Reducing resource usage is obviously equivalent to buying a bigger FPGA; if there are fewer resources then each design section will be smaller and it'll be easier to place them without overlaps.

- Timing limitations determine where Vivado can place parts of the design. If you can loosen the limitations then Vivado has more flexibility in moving sections of the design so they won't overlap.

- Clock buffers are a concern because the clock infrastructure is coarsely-grained (at least in the 7-series chips, I don't know about UltraScale). Moving a clock buffer may cause Vivado to move a whole section of the design along with it.

 

However, after all of that, it's quite possible that the design simple doesn't fit on the chip you've selected.

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