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jmpg

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04-24-2009 12:46 AM

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Registered:
03-26-2009

Hi friends,

My apologies if it’s a resolved issue previously but I haven’t found the question/answer in the forum or Internet.

I’m trying to generate a high precise clock of 45.696 MHz (for example) and I need a precision on the order of KHz (it’s not too much ). I have tried using both a Clock Generator within an EDK platform and a DCM component directly. They both generate a clock that is near to the specified but not the most precise: 45.454 MHz.

It has been proved in a Virtex 5 device (in theory, they have the best Clock Management Technology)

It happens because the DCM synthesizes the output frequency by means an integer multiplier (M) and divisor (D).

I think to solve the problem I have to generate the precise clock with custom circuit logic design. I can design a NCO that generate the 45.696 MHz clock from the system clock of 100 MHz and then, I can use it to drive a DCM component which provides its specific clock management features (clock deskew, derived clocks, etc.)

Is this possible? What problems will I have with this approach?

Does anyone have a better idea?? Please, help me!!

Thanks in advance!

Jose

1 Solution

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gszakacs

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04-25-2009 09:57 AM

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Registered:
08-14-2007

What are you really trying to do? If you need a frequency generator that gives you increments

of about 1 KHz, you could use a NCO, but remember that unless you use some sort of analog

filtering technique you will have peak to peak jitter equal to the period of the input clock to the

NCO. This would not be acceptable for driving a DCM. However if the logic that requires the

frequency can live with the jitter you may be able to use it directly.

If you only need to generate one exact frequency or a small number of fixed frequencies,

but you need a clean clock, you can cascade DCMs and PLLs in the Virtex 5. For

example you could use the FX output of a DCM to drive a PLL input and then generate

a frequency based on the product of the two M/D ratios. This gives a much larger

number of achievable frequencies, but requires some work to find the ratios by

factoring the integer ratio you desire.

HTH,

Gabor

-- Gabor

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gszakacs

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04-25-2009 09:57 AM

16,916 Views

Registered:
08-14-2007

What are you really trying to do? If you need a frequency generator that gives you increments

of about 1 KHz, you could use a NCO, but remember that unless you use some sort of analog

filtering technique you will have peak to peak jitter equal to the period of the input clock to the

NCO. This would not be acceptable for driving a DCM. However if the logic that requires the

frequency can live with the jitter you may be able to use it directly.

If you only need to generate one exact frequency or a small number of fixed frequencies,

but you need a clean clock, you can cascade DCMs and PLLs in the Virtex 5. For

example you could use the FX output of a DCM to drive a PLL input and then generate

a frequency based on the product of the two M/D ratios. This gives a much larger

number of achievable frequencies, but requires some work to find the ratios by

factoring the integer ratio you desire.

HTH,

Gabor

-- Gabor

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jmpg

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04-27-2009 01:19 AM - edited 04-27-2009 01:20 AM

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Registered:
03-26-2009

Re: Generating a High Precise clock with logic resources

Thanks a lot for your answer, Gabor.

I have generated the clock with a NCO, and in fact you are right, the jitter is equal to the period of the board clock (100 MHz). I tried to drive a DCM and I obtained the next error:

**************************

*ERROR:NgdBuild:455 - logical net 'clk_65mhz_i' has multiple
driver(s):*

* pin PAD on block
clk_65mhz_i with type PAD,*

* pin DOA<0>
on block*

* Inst_nco_clockgen
/blockXXX/SP.WIDE_PRIM18.SP with*

* type RAMB18 *

* *

*(where 'clk_65mhz_i' is a high precision clock frequency of
65.468 MHz)*

**************************

I only need to generate one exact frequency (and others multiple of this). I’ve already tried with cascade DCMs but I didn’t obtain good results (I think there were errors related to the instantiation of the DCM, the interconnection between them or something like that)

Ok, I will try this approach. I think with a frequency equals to:

*fout = fclk * M1/D1 * M2/D2 * … Mn/Dn *

It will be possible to generate a high precision and clean clock

:smileyhappy:

Best regards,

José MaríaMessage Edited by jmpg on 04-27-2009 01:20 AM

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jludvig@sbcglobal.net

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04-27-2009 09:40 AM

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Registered:
04-27-2009

Re: Generating a High Precise clock with logic resources

Hi,

it sounds like you need to use a classic PLL circuit with a VCO, a charge pump and two dividers.

The latter can be designed with FPGA resources but neither the VCO nor the charge pump can be built

succesfully with circuits available inside FPGAs. Best results can be achieved with VCXOs and RF PLLs

from e.g. Analog Devices etc.. Total cost should be less than $10 and you will get an excellent clock signal.

Alternatively an NCO with sine table and a 16 bit TxDAC plus RF low/bandpass filter plus low noise

RF discriminator can be used. The circuit is widely used in test and measurement equipment but anything

than trivial to design (even though it sounds straight forward, because of its wideband properties it is a lot

harder to clean up than the PLL with VCXO which is by almost all measures easier and better, except that

it does not have the frequency agility of the NCO.

Good luck!

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jmpg

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04-28-2009 05:17 AM

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Registered:
03-26-2009

Re: Generating a High Precise clock with logic resources

Thanks jludvig for your knowledge.

I’ve implemented a clock generator based on two cascade DCM. With only two DCM components it is possible to obtain a frequency with enough precision (error is less than 160 Hz). And this is a clean and stable clock (with a very small jitter)

It wasn’t so difficult (I can say it now), and I’ve written a matlab script to calculate the integer factor (M1/D1*M2/D2) to obtain the high precision frequency

Best regards,

José María

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using FDA tool in matlab i generated a notch filter....and the HDL code of it.Now my problem is I have to give a voice signal recorded in matlab that is ".wav" file as input to this hdl code in xilinx....how to import data from matlab...pls help me,,,,,,,

shil_pscies

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09-11-2009 01:43 AM - edited 09-13-2009 10:19 PM

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Registered:
09-11-2009

Re: how to import data to xilinx from matlab

Message Edited by shil_pscies on 09-13-2009 10:19 PM

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prabulkanth

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01-31-2012 03:49 AM

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Registered:
11-17-2010

Re: Generating a High Precise clock with logic resources

Hi José María,

i am facing trouble in generating precise clocks of 39.2832 Mhz from 100 Mhz input clock.Could you help me with how to go about this using 2 DCM's. Can you share the matlab script to find the M1,M2,D1,D2 integers to achieve this frequency

Prabul

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Ratio is 6138/15625,

2 * 9 * 11 * 31 / 5^6

------------------------------------------

"If it don't work in simulation, it won't work on the board."

rcingham

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01-31-2012 05:17 AM

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Registered:
09-09-2010

Re: Generating a High Precise clock with logic resources

2 * 9 * 11 * 31 / 5^6

------------------------------------------

"If it don't work in simulation, it won't work on the board."

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gszakacs

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01-31-2012 07:42 AM

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Registered:
08-14-2007

Re: Generating a High Precise clock with logic resources

The smallest you can make M and D for a two-DCM cascade would be 93/125 * 66/125

I don't think most DCM's allow numbers this large, but it depends on the FPGA series. The

tough part is to find another integer ratio that may not be exact, but close enough to

the desired ratio that allows smaller M and D. In general it's not a good idea to cascade

more than two DCM's because of jitter.

-- Gabor

-- Gabor

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jmpg

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02-01-2012 06:15 AM

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Registered:
03-26-2009

Re: Generating a High Precise clock with logic resources

Hello Prabul,

Depending in with Xilinx family are you using, there may be better options than 2 cascade DCM. I think 2 DCM's option is supported by Vtx4, but for newer FPGA's there are other clock components like PLL's.

Attached is the old / dirty script that I did for this calculation (with 2 DCMs). It uses brute force search of best combination (I think, I don't remember well)

Sorry, it is not commented, but it 's easy to understand :smileywink:

If you can use PLL, I think coregen provides some wizard that automatically calculates the multiplication and division factors.

Best regards,

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gszakacs

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02-01-2012 06:27 AM

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Registered:
08-14-2007

Re: Generating a High Precise clock with logic resources

**If you can use PLL, I think coregen provides some wizard that automatically calculates the multiplication and division factors.**

I'm pretty sure that the wizard only calculates factors for a single PLL or DCM. Your script is probably

better when a single ratio doesn't come close enough.

-- Gabor

-- Gabor

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If you only need to generate one exact frequency or a small number of fixed frequencies,

but you need a clean clock, you can cascade DCMs and PLLs in the Virtex 5. For

example you could use the FX output of a DCM to drive a PLL input and then generate

a frequency based on the product of the two M/D ratios. This gives a much larger

number of achievable frequencies, but requires some work to find the ratios by

factoring the integer ratio you desire.

______________________________

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zhuzhuxiao

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02-20-2012 12:11 AM

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Registered:
02-20-2012

Re: Generating a High Precise clock with logic resources

but you need a clean clock, you can cascade DCMs and PLLs in the Virtex 5. For

example you could use the FX output of a DCM to drive a PLL input and then generate

a frequency based on the product of the two M/D ratios. This gives a much larger

number of achievable frequencies, but requires some work to find the ratios by

factoring the integer ratio you desire.

______________________________

enjoy game so much!

[url=http://www.storeingame.com/]wow gold[/url] [url=ttp://www.buymaplestory.com/]Buy Maplestory Mesos[/url] [url=http://www.2joygame.com/]WOW Gold[/url]