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Adventurer
Adventurer
4,354 Views
Registered: ‎09-04-2011

Generating the global reset : ZC702 ZYNQ platform ...

Hi,

 

I have imported XPS system to ISE and I need to use the global reset. In the imported system,

 

processing_system7_0_PS_SRSTB : IN std_logic;

 

is the reset pin for processing system. However, in UCF I can only see

 

NET "PS_SRSTB"   IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C9" ;

 

1) What is the correct way of generating the global reset (in top module)?

2) If processing_system7_0_PS_SRSTB buffer the PS_SRSTB internally (in PS system), how to generate global reset?

 

Thank you.

 

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3 Replies
Adventurer
Adventurer
4,337 Views
Registered: ‎09-04-2011

Re: Generating the global reset : ZC702 ZYNQ platform ...

Hi,

 

Is it possible to make an external reset pin (to reset PL design in VHDL) from ZYNQ-7000 platform?

The PS system "Reset" block (in XPS) can't be edited.

 

Thank you.

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Adventurer
Adventurer
4,331 Views
Registered: ‎09-04-2011

Re: Generating the global reset : ZC702 ZYNQ platform ...

Hi,

 

I have found the answer and it is in,

 

LogiCORE IP Processor System Reset Module (v3.00a) datasheet.

Link : http://www.xilinx.com/support/documentation/ip_documentation/proc_sys_reset.pdf

 

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Visitor rusevm
Visitor
4,287 Views
Registered: ‎07-08-2011

Re: Generating the global reset : ZC702 ZYNQ platform ...

But that's not solving it for an ISE editor. What pin could you use/ io core to generate global reset under project navigator?

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