02-25-2013 11:15 PM
I have imported XPS system to ISE and I need to use the global reset. In the imported system,
processing_system7_0_PS_SRSTB : IN std_logic;
is the reset pin for processing system. However, in UCF I can only see
NET "PS_SRSTB" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C9" ;
1) What is the correct way of generating the global reset (in top module)?
2) If processing_system7_0_PS_SRSTB buffer the PS_SRSTB internally (in PS system), how to generate global reset?
02-26-2013 03:45 PM
Is it possible to make an external reset pin (to reset PL design in VHDL) from ZYNQ-7000 platform?
The PS system "Reset" block (in XPS) can't be edited.
02-26-2013 07:45 PM
03-31-2013 01:58 AM
But that's not solving it for an ISE editor. What pin could you use/ io core to generate global reset under project navigator?