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anshpmrl
Adventurer
Adventurer
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Registered: ‎04-07-2014

Glitch free dynamic clock divider

Hi Folks,

 

Could anyone share the Source code/docs of a Glitch free Dynamic Clock Divider implemented in RTL.

 

Thanks in advance.

Akshay.

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florentw
Moderator
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Registered: ‎11-09-2015

Hi @anshpmrl,

 

For which device?

 

A good way to do a clock divider is to use a BUFGCE primitive (see UG472 p42 and UG768 p77). Controlling the CE pin will help you to divide the clock.

You also may want to look at MMCMs in the same UGs.

 

Hope that helps,

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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anshpmrl
Adventurer
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Registered: ‎04-07-2014

Hi Florent,

 

As said, i am not planning to use any Xilinx Primitives for this purpose.

I am looking for an RTL code !.

 

Thanks

Akshay

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avrumw
Expert
Expert
6,197 Views
Registered: ‎01-23-2009

Could anyone share the Source code/docs of a Glitch free Dynamic Clock Divider implemented in RTL.

 

For what purpose? What do you want to do with this clock?

  - forward as an output to a downstream device?

  - clock internal logic?

  - use to capture input data?

  - use to drive output data?

  - use in a synchronous manner with other (non-divided) clocks?

 

The answer to these questions are very important in determining if you can do what you want to do (forget about how to do it) - particularly with your (bizarre) requirement of using no FPGA primitives. Why can't/won't you use the Xilinx primitives (that are specifically designed to deal with complex clocking systems)?

 

Avrum

muzaffer
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Registered: ‎03-31-2012

>> Why can't/won't you use the Xilinx primitives (that are specifically designed to deal with complex clocking systems)?

 

Because he wants to prototype something for an ASIC?

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anshpmrl
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Registered: ‎04-07-2014

Because he wants to prototype something for an ASIC?

 

Yes, you are right. It is for ASIC prototyping.

 

Thanks,

Akshay.

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avrumw
Expert
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Registered: ‎01-23-2009

Could anyone share the Source code/docs of a Glitch free Dynamic Clock Divider implemented in RTL.

 

As said, i am not planning to use any Xilinx Primitives for this purpose.

I am looking for an RTL code !.

 

So. No.

 

Take a look at this post on the problems of converting ASIC style clock structures to FPGAs.

 

Avrum

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anshpmrl
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Registered: ‎04-07-2014

Hi Folks,

 

I managed to solve the issue by developing a wrapper around the Clock divider.

Whenever a change in divider value is detected, the wrapper logic will gate the output clock(Latch based clock gate) and re-initialize the divider counter , then load the new divider value to the Clock divider, then disable the clock gating after few cycles of new clock. So final output clock will be glitch free.

 

Thanks

Akshay.

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avrumw
Expert
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Registered: ‎01-23-2009

I repeat my earlier questions (which you never answered) - what do you want to do with this divided clock.

 

If you expect this clock to be able to work synchronously with any other clock (for example, the base clock that is used to clock the divider), then it pretty much won't - the skew between the base clock and the generated clock will be significant - particularly since you pretty much have to drive this divided clock back to a BUFG in order to clock any internal logic.

 

The tools will (or at least can) understand the behavior of the clock (you should have a set_generated_clock on the output of the divider), but the tool will recognize the huge clock skew between this clock and the base clock. At very low frequencies (of the base clock), it may be able to do sufficient hold time fixing without totally breaking the setup times, but even at moderate frequencies, this will become impossible.

 

Again, you can't simply replace ASIC clocking structures with FPGA fabric based RTL solutions; while they may work functionally, the timing characteristics quickly make these systems non-viable.

 

Avrum

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anshpmrl
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Registered: ‎04-07-2014

HI Avrum,

 

I agree with your comments. In our case, all the clocks should be synchronous (input to the divider as well as the o/p of the divider).

In ASIC, the tool was able to meet timing. Also, this scheme is functionally working on FPGA as well.

 

Thanks,

Akshay.

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avrumw
Expert
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Registered: ‎01-23-2009

I agree with your comments. In our case, all the clocks should be synchronous (input to the divider as well as the o/p of the divider).

In ASIC, the tool was able to meet timing. Also, this scheme is functionally working on FPGA as well.

 

In an ASIC, there is no problem with meeting timing in a system like this; the clock insertion tool balances the loads, even between the gated and ungated (divided) loads.

 

This is not the case in an FPGA.

 

Do you have proper constraints on your gated clock (a create_generated_clock)? If you are crossing synchronously between the domains have you NOT put the clocks in different clock groups (if you are crossing synchronously between them, you cannot put them in separate clock groups or define paths between them false or maxdelay)? Does your design pass timing analysis (i.e. are there no timing violations)?

 

If you have done all of the above and it meets timing, then it should work in the lab. But this is surprising; designs like this are structurally flawed for implementation in an FPGA. You may be able to get them working at low clock speeds, but this is not a recommended approach.

 

If you have gone to the effort of wrapping the clock divider (presumably specifically for the ASIC implementation), then why not just generate a custom version of this wrapped divider for the FPGA. Yes, it is always desirable to have the same RTL code for the ASIC and the FPGA, but in cases like this you are better off having customized code for the two implementations rather than having unsuitable code for your FPGA.

 

If your design does not meet timing, then, in spite of the fact that it might work in the lab, you will be working with a flaky design. At any moment, due to the combination of Process, Voltage and Temperature, your design will fail. It may do so intermittently and anywhere from extremely frequently to extremely rarely. Any bug you observe in the "ASIC prototype" may be a real bug, or may be a symptom of the fact that you are using an un-timed design in the lab; this is a bad place to be for an "ASIC prototype"...

 

Avrum

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