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Observer
Observer
5,776 Views
Registered: ‎02-16-2011

HDL and System generator

Hi everyone,

 

we all knows system genreator could generate hardware languages (verliog and VHDL). But my question is that:

 

 Compare to professional HDL programmers,  how good about these codes generated by system generator, which one is more  efficency?

 

Regards

 

Ryan

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Teacher
Teacher
5,767 Views
Registered: ‎08-14-2007

Hi Ryan.

I understand your intent, but for sysgen this question does not really make sense.

(Take a look at sysgen code, there's not much behavioral stuff in it.)

 

The point is that sysgen (with the simulink schematics) basically configures cores and instantiates these in a netlist.

Let us ignore fo the moment, that a programmer can not write down all the coregen functions immediately from scratch.

Even then typing down all the instantiation port lists would be a waste for a (hopefully well paid) professional HDL designer.

Also working with Coregen interactively is very time consuming.

From this point of view sysgen just increases the productivity for DSP designs.

Then comes the next thing: The connectivity to Matlab allows for very intense testing and result analysis.

How would a designer deal with this if all he could do is to write a HDL Testbench?

He had to write tons of code that cold be done better with just a few matlab commands.

 

Of course sysgen has its weak points. That is mainly when you need to do some complex datapath controll.

But how's that done? Mostly by designing some FSM which then is hold in a Black box block or (for the non-HDL guys) in a MCode block. But here we are back to the editor tool, so it makes no difference if you are a plain HDL designer or using sysgen.

 

The more important point beyond the question of someones "syntactical skills" in any technical language is: How good is the designer in understanding and implementing a system.

Have you read acros some forum posts?

What good is  a professional HDL "programmer" if he doesn't know how a FFT works, what the impacts of the sampling frequency on some signal properties are and.... what a UART is and how to use it.

 

Someone who has a good understanding of the System (DSP theory, Computer architecture, numerical math), the underlying hardware (FPGA), and the tools and is still able to overlook these manyfold topics is more valuable than a mere HDL "programmer" who just knows syntax. Today there's more needed than just HDL and digital design skills.

 

Want to know about the future: Take a look at the Xilinx Vivado software. Keywords: IP-centric etc. because a single person is no longer able to fill actual FPGAs just by writing HDL code.

Remember the past. How many engineers were involved in designing a fully filled 19" rack (I mean the big ones, about 2m high) . What has been done then with discrete logic now goes in a single chip. While the tools have increased productivity the complex systems still demand for teams. Lonely heroes will lose in the competition.

 

Regards

  Eilert

 

 

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Historian
Historian
5,760 Views
Registered: ‎02-25-2008


@eilert wrote:

 

Want to know about the future: Take a look at the Xilinx Vivado software. Keywords: IP-centric etc. because a single person is no longer able to fill actual FPGAs just by writing HDL code.

  


That's an absurd assertion. 

 

The assumption inherent in that "a single person is no longer able to fill actual FPGAs just by writing HDL code" is that every design will be the sort that fills a 2,000,000 LUT FPGA doing all sorts of standardized things for which cores are available.

 

My guess is that the great majority of FPGAs are along the lines of what I do -- special-sauce data handling and control, the kind of stuff for which no IP cores exist, and it all fits into one of the smaller or moderate Spartan 3 or 6 devices, or perhaps the smallest Virtex device because of the need for high-speed serial I/O that's on the newest ADCs.

 

Is there really that big a market for embedding an ARM into an FPGA? What are people doing with that, which can't be accomplished by putting a (much cheaper) standalone ARM or PPC chip next to a (much cheaper) smaller FPGA? The bonus, of course, with the separate parts is that we're not screwed by the tools or the cores, and anyone who's used the EDK knows what I'm talking about. 

 

(I know a guy who's doing work for an observatory, doing lots of FFTs in a super-duper-big FPGA, but it's a one-off instrument so the quantity is pretty much single digit, and the processor handling the control is not in the FPGA.)

----------------------------Yes, I do this for a living.
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Teacher
Teacher
5,751 Views
Registered: ‎08-14-2007

Hi Bassman,

agreed, the term "actual FPGAs" was choosen too carelessly. Sorry for that.

Of course I refered to the big ones and how the device sizes grew within the last years.

 

(If written some long answer, but the forum system busted it. :-(

 That happens when writing a post takes a little longer.)

 

As you could see in my last post I was talking about systems that filled up large 19" racks, so it's different from the stuff you do which would compare to one or more PCBs inside the mentioned rack, capable of holding some dozend PCBs or more. (And I mean racks of the DSP/Microprocessor era, not just plain MSI logic devices)

 

Kind regards

  Eilert

 

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Visitor
Visitor
5,705 Views
Registered: ‎05-21-2012

System Generator is nothing more than schematic entry using primitives and coregen cores.  sure you can also do some limited M-file stuff too (and that's better than connecting wires all over the place, imho).  

 

its a throw back to Logic Blocks in Viewdraw pre-V2 parts.

 

I started my journey in the world of FPGAs using VHDL.  Having to use Simulink/SysGen is slow and cumbersome and full of "cores", which I dislike using in my designs unless I must (FIFOs, etc).  The tool just freezes when I try to add the block box component, so I can't even try and integrate "real" VHDL with an existing simulink design.

 

not to mention tools like these force vendor lock in and a total redesign is necessary if you had to port vendors.

 

and missing are some awesome (V)HDL language features that can make code easily reusable, compact, readable and portable.

 

and a model is not very SCM tool (CVS, SVN, Hg, etc, etc) friendly and make version control difficult or impossible.  no direct way to compare two versions of a design either.

 

I have NO problems designing/maintaining entire systems (multiple boards) in (V)HDL (usually working with system engineer/architect).  Sure, not evey digital designer is also a system engineer, but many do wear that hat and wear it well.

 

you also don't "program" HDL, you design/describe an architecture with it.   these tools spit out structural HDL or binary netlists, but nothing readable.

 

on the flip side, it is a good prototyping tool for a system engineer (as opposed to pure matlab) to use when working with a hardware engineer.  the ability to gloss over vector precision/bit widths at first is nice too (but at the loss of control).

 

the best place I see this tool is in verification.  If a traditional simulation could be integrated with the matlab/simulink environment, maybe the quality and degree of verification could be improved and reduce design iterations and number of bugs that slip through and are found in the field in real HW.  the same (or very similar) verification environment could be used for system design, HDL simulation and real HW.

 

stepping off the box.

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Observer
Observer
5,246 Views
Registered: ‎02-16-2011

Hi Eilert,

Thanks for answering my question. I understand your means and it helps.

Best,

Ryan
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Observer
Observer
5,247 Views
Registered: ‎02-16-2011

"The tool just freezes when I try to add the block box component, so I can't even try and integrate "real" VHDL with an existing simulink design."

What do you mean by this? the black box works I think, although it has to obey some design rules.

"missing are some awesome (V)HDL language features that can make code easily reusable, compact, readable and portable."

Could you give me a small example fo this? Probably I'm not a experienced hardware architecture designer. i don't know too much VHDL awesome features.

Best,

Ryan




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