07-14-2009 02:58 AM
I have implented an interface module (VHDL), which will be on a Spartan-3a FPGA, this module is interfaced with an external TI-ADC which gives me a 24 bit digital value for an analogue signal applied.
My module works at 50Mhz frequency(Internal) and the ADC works at lower frequency of 20 Mhz and the serial transfer rate of the 24 bits will also be at 20Mhz speed.
I foresee a problem here, as my module is working at higher speed will I lose out on any bits which the ADC is sending?
How should I over come this problem? Apply same clock to both? I cant apply 50Mhz to ADC as it is against its specifications, so have to bring down the clock speed of my module. Or will a bufffer in between will do?
I'm a newbie in hardware design, please explian to me your solutions in a little detail.
07-14-2009 05:35 AM
But the problem is that the ADC is that it is not giving out its clock.....its using its clock internally.....
But the ADC has an option to give it an external clock. So, I feel like bringing down the speed of my module from 50MHz to 20MHz..... but I dont have a clock source with me.... is there a way I can take the on board 50 MHz clock down-frequency it to 20 MHz and re-apply as a clock to both FPGA and ADC. That way both my module and ADC will be in synch?
Can you suggest how to do this? Any docs?
07-14-2009 07:51 AM
07-21-2009 11:43 PM
hi vikram ,
with the provided infomation i dnt find ny problem in design as u r working on adc +fpga.
adc sends the serial data at 20 mhz ,u can have a clk divider circuit in ur fpga ,and scale down frequency to 20mhz this way ur fpga is internally working on 20mhz and nw u cn apply this as serial clock to adc.if there is any other processing at 50 mhz then u have to use buffer to store adc data . reply if this helps u ,or otherwise explain the problem further