04-23-2010 02:42 AM
I'm working on a small project and i'm a begginer in VHDL.
I am using a Spartan 2 and I'm clocking it at a rate of 32MHz. I then have scaled the clock down to 8 MHz.
I now want to use my scaled clock (8MHz clock) to clock my implemented design.
In my VHDL code I have decleared the scaled clock as a buffer wich is than synthesised by Xilinx ISE 6.2 as an output!
I have been reading on different online posts that I should declare the scaled clock as an IBUF and than copy it to a GBUF in order to use it as a clock.
I am very unclear with this, do I declare it as a GBUF in my VHDL code or do I make these changes in the constrain file? What would be the correct syntaxing for it?
Please help as I'm stuck, can't get my head around this!
Thanks in addvance
04-23-2010 05:34 AM
when you are designing in VHDL (or verilog) it's not necessary to do anything at all, but assign the clock net to the desired pin in the UCF file.
XST automatically recognizes this net as a clock net and inserts the correct buffers.
Manual instantiation of clock elements is only necessary when dealing with DCMs, and even then only when you want to do special things.
To be sure, wether your design was implemented as desired or not, you can take a look at the final design in the FPGA-editor.
Have a nice synthesis