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Anonymous
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Help needed to get understanding

Hi,

           Here i am writing counter which counts the value from 0 to 7 on every rising edge clock of  8 bit each.But i want to increment the counter after serializing first value(first count).But exactly i am not able to get.

ex: when reset is '0' counter is also X"00".So i want to serialize this data then i want to increment it to X"01".After serializing this parllel data i want to increment the counter.This process is continue upto "X07".But counter is incrementing on every rising edge clock.So i am not able to serialize all the data.If i put delay counter is not incrementing only.I think some understand problem i had in my code.Please help me to solve this problem.

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity test_bench1 is
 end test_bench1;


architecture  behav of test_bench1 is

 signal serial_data_s        : std_logic;
 signal temp             : std_logic_vector(7 downto 0) ;
 signal resetn_s        : std_logic := '0';
 signal clk_26MHz_s        : std_logic := '0';
 signal clk_s             : std_logic := '0';
 signal    temp_s            : std_logic_vector(7 downto 0);
 
 begin
process(clk_s,resetn_s)        
 begin
 if(clk_s'event and clk_s ='1') then
   if(resetn_s ='0')then
       temp                      <= (others => '0');
       temp_s                 <= (others => '0');
       serial_data_s      <= '0';
       
   else
     if(temp = X"07") then
         temp                    <=  (others => '0');
     else
         temp                    <=  temp + '1';
         temp_s               <=  temp;
         serial_data_s    <=  temp_s(7);  
         for i in 6 downto 0 loop
             if(clk_s'event and clk_s = '1') then
             temp_s(i+1)          <=  temp_s(i);
             --serial_data_s    <=  temp_s(i);
             end if;
         end loop;
     end if;
  end if;
end if;
end process;
              
resetn_s          <= '1' after 40 ns;
clk_26MHz_s        <= not clk_26MHz_s after 18.796 ns;
clk_s          <= clk_26MHz_s ;

end behav;

 

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