07-26-2019 04:54 PM
Hello, my company is evaluating Zynq Ultrascale+ MPSoC products for our next generation of power electronics control systems. We have little experience with FPGA, but have purchased several dev kits over the past years and are trying to come up the curve. One missing link on these devices seems to be the ability to generate high resolution PWM signals.
In the power and performance range we are operating we will require a minimum of 15-bit PWM resolution at a PWM frequency of 200kHz (~150ps edge resolution). Also the internal clock used to generate the PWM outputs must be symmetrical (eg triangle) and variable frequency.
Many modern DSPs and MCUs (TI, Infineon, etc) include on-chip peripherals with delay taps to accomplish this so you don't have to use a 3+GHz clock. However we are trying to capture the performance advantages of FPGA and hence our interest in Zynq Ultrascale.
I've done a fair bit of research and found multiple threads asking similar questions. Most responses are along the lines of "that's a challenge" or "look at using a DLL or OSERDES", but very little detail on how this could be accomplished practically. As this feature has been available in other products for over a decade now, I hope I'm missing something. Here's a comment thread from almost 10 years ago!
We have also considered using Zynq but adding an external DSP solely for PWM generation. The problem is getting in/out of the DSP results in relatively large delays (microseconds) that nullify the performance benefits from going to FPGA in the first place, not to mention the challenge of synchronizing the two chips for A/D sampling, etc.
All of that to ask, is there any practical way to acheive 150ps edge resolution on a variable frequency clock using Ultrascale or any other Xilinx SoC devices? And if the solution involves adjusting delay lines (eg DLL), can they be modified fast enough to allow command updates every ~2.5us?
07-28-2019 04:49 AM
Achieving 150ps edge resolution for PWM is almost within reach using the brute-force approach and the Xilinx UltraScale+ FPGA. That is, with UltraScale+, we can almost change the state of a digital output every 150ps.
From the top-of-the-line Virtex-UltraScale+ datasheet, DS923, I find the limiting factor to be the clock-distribution buffers (Table 32) which max out at 891MHz. This means we can create a DDR output from the FPGA (using either ODDR or OSERDES blocks) that changes on both the rising and falling edge of the 891MHz clock. Thus, the state of the digital output changes at a rate of 2x891=1.782GHz (ie. every 561ps).
If we use 8:1 OSERDES, then the FPGA fabric can be clocked at 891/4=222MHz. Thus, decisions about PWM width can be made in a few cycles of the 222MHz clock – far faster than the needed update rate of every 2.5us.
This brute-force approach to PWM also makes the needed symmetric-PWM easy to achieve.