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Visitor pacala
Registered: ‎04-09-2013

High speed ADC FIFO Design Tips

I'm new to the world of high speed ADC's and FPGA and this is more of a system design question than a technical dive.


I have an application requiring a 1 GSPS 8-bit ADC with dual 500 MHz data output that must send data to a high performance DSP for signal analysis. The DSP is capable of 500MHz data interfacing but I don't want to tie up its I/O. The analog signal into the ADC contains infrequent pulses that I want to capture and timestamp. There is an opportunity for a 10x data reduction to the DSP if I only pass along data associated with the pulses. 


This sounds like a job for a FIFO that has an intermediate step that compares the buffered values to a threshold. All sample values below the threshold are discarded and samples with values above the threshold (and perhaps the several samples to either side) are passed along to the DSP for analysis. One additional issue is that I need to timestamp the samples based on a start signal from the DSP and a counter from the FIFO.


As I am new to both FPGA and high speed data aquistion, I was hoping to get some advice regarding what family of FPGA would be required to meet my data throughput and space requirements. I estimate that the size of the FIFO needs to be no larger than 512 kbits. From what I have read, it seems I might be able to get away with something from the Spartan-II family. Thanks for the advice!

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Registered: ‎08-14-2007

Re: High speed ADC FIFO Design Tips

Spartan II is very old and won't even get close to 500 MHz.  You should probably look at

something in the 7-series if you need to run 500 MHz through the part.  Spartan 6

could handle 500 Mbps I/O and use the internal SERDES components to run with

wider data at 250 MHz internally.  Then all your logic would need to work on a

4-sample-wide data path.  Is the ADC output LDVS?  If it is instead some single-ended

I/O standard like HSTL you may have a harder time with the I/O at this speed.

-- Gabor
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