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Visitor
Visitor
3,624 Views
Registered: ‎04-19-2009

How To Allocate DDR2 SODIMM pins to Vertix-4 FX60 Banks?

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Now I have a design that need to add a DDR2 SODIMM to Vertix-4 FX60 device,and I have heard that the Data pins and Address pins allocation must be cared, But I don't know the details,somebody else knows it?

another question is that I can't allocate all the tracks to two banks like on the board ML410,now at three banks ,will it have problem to run?

Thank you !

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Visitor
Visitor
4,293 Views
Registered: ‎04-19-2009
I have seloved the problem through make an exzample project created by MIG,and changed the UCF file to my allocated pins, then compile it in ISE,and it successed.My pin allocate in bank7, bank9 and bank11.and  DDR data lane0 to lane 3 all allocate at bank 9 ,and data lane 4 to data  lane 7 all allocate at bank 7 and most of the address and cmd lines are allocated  in bank11.

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Observer
Observer
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Registered: ‎03-02-2009

Hi,

 

you are rihgt. For high speed memories we need to take special care. Data lines and address lines are routed to particular banks in FPGA. For details refer MIG user guide. If is always recommended that you follow the UCF generated by MIG.

 

Regards,

Onkar 

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Highlighted
Visitor
Visitor
4,294 Views
Registered: ‎04-19-2009
I have seloved the problem through make an exzample project created by MIG,and changed the UCF file to my allocated pins, then compile it in ISE,and it successed.My pin allocate in bank7, bank9 and bank11.and  DDR data lane0 to lane 3 all allocate at bank 9 ,and data lane 4 to data  lane 7 all allocate at bank 7 and most of the address and cmd lines are allocated  in bank11.

View solution in original post

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