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garengllc

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09-28-2015 11:27 AM

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Registered:
04-10-2012

How best to do inner product of two vectors

I am using Vivado and am attempting to compute the dot product of two vectors, but seem to be getting stuck in the weeds.

I have sync_pattern_size elements (lets say that is 8 for simplicity sake) in one vector, and a much larger number of elements in a circular vector that I want to multiply agasint. Where I keep getting wrapped around the axle is how to handle the sum of the products in parallel.

My plan was:

reg [15:0] index2 = 8'd0;

reg signed [31:0] corr_sum;

reg signed [31:0] corr_sum_reg;

reg [31:0] abs_corr_sum = 32'd0;

reg [31:0] abs_corr_sum_reg = 32'd0;

always @*//(posedge clock) begin // for each incoming sample abs_corr_sum = 32'd0; sample_data_buffer_I[sample_index] = i_tdata[15:0]; sample_data_buffer_I[circ_buf_size + sample_index] = i_tdata[15:0]; sample_data_buffer_Q[sample_index] = i_tdata[31:16]; sample_data_buffer_Q[circ_buf_size + sample_index] = i_tdata[31:16]; for (index2 = 0; index2 < sync_pattern_size; index2 = index2 + 1'b1) begin corr_sum = sample_data_buffer_I[index2+sample_index+circ_buf_size-sync_pattern_size] * sync_pattern_I[index2] + sample_data_buffer_Q[index2+sample_index+circ_buf_size-sync_pattern_size] * sync_pattern_Q[index2]; if(corr_sum[31] == 1'b1) begin abs_corr_sum = abs_corr_sum + corr_sum; end else begin abs_corr_sum = abs_corr_sum + corr_sum; end end

end

And then in a second block:

always @(posedge clock) begin corr_sum_reg <= corr_sum; abs_corr_sum_reg <= abs_corr_sum; end

But this doesn't seem to work right when the corr_sum is a negative value. I know that my cheapo absolute value convertion should be fine, so I think I am scewing up somewhere else trying to parallelize this dot product operation. Is there any easier way to go about this?

3 Replies

morgan198510

Voyager

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09-28-2015 04:55 PM - edited 10-30-2015 08:42 PM

8,863 Views

Registered:
04-21-2014

wooshh, answer deleted because it was ignored.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***

garengllc

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09-29-2015 05:47 AM

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Registered:
04-10-2012

A lot of other issues I'd comment on after asking questions, but you didn't ask for that kind of feedback.

I'm sorry, I'm not sure what you mean by this?

if(corr_sum[31] == 1'b1) begin abs_corr_sum = abs_corr_sum + corr_sum; end else begin abs_corr_sum = abs_corr_sum - corr_sum; end

I had an error when I was was cleaning up my copy and paste, you are right, I didn't have my original if-statement right, here is what I have that isn't working:

//this is my quick and dirty abs(corr_sum) summer if(corr_sum[31] == 1'b1) begin $display("NEG:",abs_corr_sum,"+", ~corr_sum+1,"=", abs_corr_sum + ~corr_sum+1); abs_corr_sum = abs_corr_sum + ~corr_sum+1; $display("NEG:",abs_corr_sum); end else begin $display("POS:",abs_corr_sum,"+", corr_sum,"=", abs_corr_sum + corr_sum); abs_corr_sum = abs_corr_sum + corr_sum; $display("POS:",abs_corr_sum); end

morgan198510

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09-29-2015 09:17 AM - edited 10-30-2015 08:42 PM

8,841 Views

Registered:
04-21-2014

wooshh, answer deleted because it was ignored.

***Many of us who help you are just FPGA enthusiasts, and not Xilinx employees. If you receive help, and give kudos (star), you're likely to continue receiving help in the future. If you get a solution, please mark it as a solution.***