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Visitor xmuszq
Visitor
6,845 Views
Registered: ‎11-28-2012

How can I create an signal like this?(setup time and hold time)

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Dear all,

 

I need to synchro 4 ADCs with a positive pulse. In datasheet of ADC, it says that the falling edge of this pulse should meet the setput and hold time(Please see the attachment).

I am not sure how to create an pulse like this.

1. it is a vertex 4 FPGA, is possible to work with 1.5GHz clock and create a pulse?

2. the setup and hold time of the sync pulse is refered to the clock input to ADC instead of input to FPGA(although they are from the same clock source)

 

Could you give me some ideas? thanks so much!

setupandholdtime.PNG
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1 Solution

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Historian
Historian
9,023 Views
Registered: ‎01-23-2009

Re: How can I create an signal like this?(setup time and hold time)

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Now the answer is "maybe", but its not going to be easy... (leaning to probably not).

 

You haven't told us what the setup and hold time requirements around the 1.5GHz clock are, but the whole clock period is only 667ps - even if the SU/H are small in comparison, getting a signal synchronized to within less than 500ps is probably beyond the capabilities of the FPGA - particularly an old one like a Virtex-4.

 

For sure you will need to use a DCM with external feedback (see ug070, figure 2.9 - attached). This will allow you to create an internal clock that is at the "right" time to make the rising edge of the external feedback clock occur at the same time as the incoming 300MHz clock (so it will be synchronous with the 1.5GHz clock). However, this feedback mechanism has some phase error and jitter - some of these numbers are in ds302:

   - CLKIN/CLKFB phase error (CLKIN_CLKFB_PHASE): +/-120ps

   - CLK0 Jitter (CLKOUT_PER_JIT_0): +/-100ps

 

Add these two (alone) together, and you hae an uncertainty of +/-220ps - this is 440ps of uncertainty in your 667ps bit interval.

 

Now that we have an internal clock that can generate an external clock that is syncronized to the input clock, we can use this internal clock to drive a 2nd ODDR which generates the required pulse.

 

However, we need to think about signal integrity. The 300MHz clock is a relatively fast clock - the edge shape of this signal is going to be quite different than the pulse you are going to generate. You should be able to minimize this effect by generating your pulse so that it has similar characteristics to the clock - i.e. is only asserted for 1/2 of a clock cycle. To do this with the ODDR mentioned above (for generating the data), connect the D1 to a signal that is asserted for one internal clock (when you want to generate the pulse) and D2 tied to ground (or vice versa). While this will be the "closest" to the clock in terms of pulse shape, this is still not a "clock" and hence will have a different edge rate than your clock. To really understand how much uncertainty this will introduce, you would need to do Spice (or at least IBIS) simulations of the pad.

 

Then there is routing delays...

 

Finally there is the required setup and hold time requirement of the ADCs.

 

It seems unlikely that all of this is going to fit in one 667ps window.

 

Even if it does, now we need to generate the output a the correct phase. Luckily, we can adjust the phase of the internal clock using the fine phase shifting of the DCM - this is controllable in increments of CLKIN_PERIOD/256 - or 13ps in your case. This will allow us to get within 13ps of the correct phase - in the worst case though, we could be "off" by 1/2 of that, adding another 6ps to the phase error.

 

So, all told, this architecture is close to meeting your needs, but I don't think its close enough - and this is the best that a Virtex-4 can do...

 

Why are you looking at a Virtex-4, rather than a newer device? Newer devices (like the Virtex-7) have MMCMs (which are PLLs), which might be able to get a little closer (but that's not guaranteed).

 

Avrum

ClkExtFB.JPG
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6 Replies
Scholar austin
Scholar
6,842 Views
Registered: ‎02-27-2008

Re: How can I create an signal like this?(setup time and hold time)

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x,

 

First answer:  no, the V4 can not process or use a 1.5 GHz clock (too fast).

 

Given that answer, then the second answer is easy: I don't see a way to do this with a V4.

 

Even with a V7, I think this would be very tricky (perhaps not possible).  You may need some PECL logic exteranal to the FPGA to generate the sync pulse.

 

And, I would never drive the ADC clock from a source from the FPGA!  The clock needs to be extremely free of any jitter, so it is best to come directly from the clock source buffer to the ADC.  You may also buffer the clock and deliver it to the FPGA if it is required there (but the FPGA should not source the clock due to added jitter concerns).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Historian
Historian
6,840 Views
Registered: ‎01-23-2009

Re: How can I create an signal like this?(setup time and hold time)

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The short answer is "No".

 

A 1.5GHz clock is WAY too fast for a Virtex-4 - its even too fast for a Virtex-7. None of the clocking resources (or flip-flops in the design) will operate anywhere near this speed. In the fastest speed grade (-12) the global clock is limited to 500MHz, and the I/O clock network to 710MHz.

 

Avrum

 

 

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Visitor xmuszq
Visitor
6,826 Views
Registered: ‎11-28-2012

Re: How can I create an signal like this?(setup time and hold time)

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Dear Austin,

 

It seems that it's impossible to do that now. If that is the case, I use lower frequency clock, 300MHz for example,  to generate the positive pulse, is that possible to meet the setup and hold time?(Note: the 1.5GHz and 300MHz are generated by the same clock buffer chip and they are synchronized). See the updated diagram. 

Thank you so much!

nn.PNG
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Visitor xmuszq
Visitor
6,825 Views
Registered: ‎11-28-2012

Re: How can I create an signal like this?(setup time and hold time)

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Dear Avrum,

I got. Thank you so much! and could you see my updated diagram? Is that possible in that case?
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Historian
Historian
9,024 Views
Registered: ‎01-23-2009

Re: How can I create an signal like this?(setup time and hold time)

Jump to solution

Now the answer is "maybe", but its not going to be easy... (leaning to probably not).

 

You haven't told us what the setup and hold time requirements around the 1.5GHz clock are, but the whole clock period is only 667ps - even if the SU/H are small in comparison, getting a signal synchronized to within less than 500ps is probably beyond the capabilities of the FPGA - particularly an old one like a Virtex-4.

 

For sure you will need to use a DCM with external feedback (see ug070, figure 2.9 - attached). This will allow you to create an internal clock that is at the "right" time to make the rising edge of the external feedback clock occur at the same time as the incoming 300MHz clock (so it will be synchronous with the 1.5GHz clock). However, this feedback mechanism has some phase error and jitter - some of these numbers are in ds302:

   - CLKIN/CLKFB phase error (CLKIN_CLKFB_PHASE): +/-120ps

   - CLK0 Jitter (CLKOUT_PER_JIT_0): +/-100ps

 

Add these two (alone) together, and you hae an uncertainty of +/-220ps - this is 440ps of uncertainty in your 667ps bit interval.

 

Now that we have an internal clock that can generate an external clock that is syncronized to the input clock, we can use this internal clock to drive a 2nd ODDR which generates the required pulse.

 

However, we need to think about signal integrity. The 300MHz clock is a relatively fast clock - the edge shape of this signal is going to be quite different than the pulse you are going to generate. You should be able to minimize this effect by generating your pulse so that it has similar characteristics to the clock - i.e. is only asserted for 1/2 of a clock cycle. To do this with the ODDR mentioned above (for generating the data), connect the D1 to a signal that is asserted for one internal clock (when you want to generate the pulse) and D2 tied to ground (or vice versa). While this will be the "closest" to the clock in terms of pulse shape, this is still not a "clock" and hence will have a different edge rate than your clock. To really understand how much uncertainty this will introduce, you would need to do Spice (or at least IBIS) simulations of the pad.

 

Then there is routing delays...

 

Finally there is the required setup and hold time requirement of the ADCs.

 

It seems unlikely that all of this is going to fit in one 667ps window.

 

Even if it does, now we need to generate the output a the correct phase. Luckily, we can adjust the phase of the internal clock using the fine phase shifting of the DCM - this is controllable in increments of CLKIN_PERIOD/256 - or 13ps in your case. This will allow us to get within 13ps of the correct phase - in the worst case though, we could be "off" by 1/2 of that, adding another 6ps to the phase error.

 

So, all told, this architecture is close to meeting your needs, but I don't think its close enough - and this is the best that a Virtex-4 can do...

 

Why are you looking at a Virtex-4, rather than a newer device? Newer devices (like the Virtex-7) have MMCMs (which are PLLs), which might be able to get a little closer (but that's not guaranteed).

 

Avrum

ClkExtFB.JPG
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Visitor wangya1988
Visitor
6,299 Views
Registered: ‎08-26-2011

Re: How can I create an signal like this?(setup time and hold time)

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Dear Avrum,
Here is my question.

I need to synchro 4 ADCs with a positive pulse too. In datasheet of the ADC, it says that 'the FPGA must be able to manage the difference in clock delay through the ADCs in order to correctly capture the data'. In the same document, it tells me to read XAPP1064. I have read XAPP1064 and XAPP1071, but they are both about applying ISERDES to ADCs with serial interfaces. However, in my board, the ADC is ISLA214P50 and the output is parallel. How can Ihandle the same question in my board? Do I still have to use 'ISERDES'? Could you give me some ideas? Thanks very much.

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