cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
wangzhibin
Observer
Observer
5,502 Views
Registered: ‎03-19-2013

How to Set AXI Video DMA for Handling FSYNC

Hi

 

Recently, i met a problem about axi vdma fsync setting.

 

In my project, I want to use one AXI VDMA and AXI Pcore for algorithm accelerating on Zedboard. My data flow is DDR->VDMA MM2S-> PCORE->VDMA S2MM->DDR

 

if fsync = 0, axi vdma runs in free, VDMA and PCORE runs OK. Moreover, according this recommendations http://www.xilinx.com/support/answers/53281.html, set FSYNC = 3,  C_USE_FSYNC = 3 and change the S2MM_DMACR register to 0x10043, the results are error. i upload my EDK project.

 

 

------------SW-------

 

The registers status is here(the hsize = 316*16,  vsize = 252):


VDMA WRITE Channel Status:
         PARKPTR        = 0x00000000
        ------------------
         S2MM_DMACR       = 0x00010043
         S2MM_DMASR       = 0x00010000
         S2MM_STRD_FRMDLY = 0x13C0
         S2MM_START_ADDR0 = 0x10000000
         S2MM_HSIZE       = 316*16
         S2MM_VSIZE       = 252
         ----------------
         S2MM_HSIZE_STATUS= 0x00000000
         S2MM_VSIZE_STATUS= 0x00000000
         ----------------

VDMA READ Channel Status:
         PARKPTR          = 0x00000000
        ------------------
         MM2S_DMACR       = 0x00010003
         MM2S_DMASR       = 0x00010000
         MM2S_STRD_FRMDLY = 0x13C0
         MM2S_START_ADDR0 = 0x12000000
         MM2S_HSIZE       = 316*16
         MM2S_VSIZE       = 252
         ----------------

 

Is there any problem about the VDMA configuration?

 

Best Regards!

Tags (2)
0 Kudos
4 Replies
bwiec
Xilinx Employee
Xilinx Employee
5,489 Views
Registered: ‎08-02-2011

What exactly is the problem? I don't see any errors being reported...
www.xilinx.com
0 Kudos
wangzhibin
Observer
Observer
5,480 Views
Registered: ‎03-19-2013

The output data form pcore processed is error When setting FSYNC = 3, but output data from pcore processed is correct when setting FSYNC = 0.

 

I suspect the problem may be the vdma configuration.  

0 Kudos
bwiec
Xilinx Employee
Xilinx Employee
5,471 Views
Registered: ‎08-02-2011

Well, the recommendations in that AR are based on some assumptions about your design. There are certainly use cases where it makes more sense to set C_USE_FSYNC parameter to something different.

My question is: if setting it to 0 works, why not just stick with that?
www.xilinx.com
0 Kudos
wangzhibin
Observer
Observer
5,459 Views
Registered: ‎03-19-2013

Thank you for reply. First, let me introduce my project as shown in the image.vdma2.png 

 

 

 

 

Now setting FSYNC = 0 for vdma0 and vdma1, i just use nano_sleep for waiting vdma I/O  communication, it works OK. but there are some bugs.

 

 Problems:

 1. When my pcore have high latency, the vdma s2mm channel transfers the unexpected results. For example, when i intergrat two pcores into only one pcore, unfortually, the results are not proper.

 2. Sometimes the bottom few lines are not proper, sometimes it works OK. 

 

So i think FYSNC = 3 is a better mode for my project, and I try to debug VDMA FSYNC=3 mode. 

 

 

 

0 Kudos