cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
10,746 Views
Registered: ‎11-23-2013

How to Synchronize clocks between multiple MMCM

Jump to solution

Hello,

We know all the output clocks in one MMCM could keep fixed phase relationship. But how to synchronize clocks between multiple MMCM?

 

For example, clka and clkb are of the same frequency(100MHz) and phase, clka feeds MMCM1 and clkb feeds MMCM2.

clka_o is the output of MMCM1 with frequency equal to 5MHz, and 90 degree phase shift.

clkb_o is the output of MMCM2 with frequency equal to 5MHz, and 45 degree phase shift.

 

If the two MMCM lock at the same time and their post divider begin to divide the VCO clock simultaneously, the synchronization can be achieved. But I doubt that.

 

Does who know how to do?

 

Thank you!

Tags (2)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Scholar
Scholar
18,382 Views
Registered: ‎02-27-2008

OK,

 

For the non-frequency modified outputs (CLK0), MMCM's driven by the same clock will be in sync.  The CLKDV, CLKFX, are not guaranteed to be in phase (as their state machines may have been reset at different times.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

4 Replies
Highlighted
Scholar
Scholar
10,700 Views
Registered: ‎02-27-2008

c,

 

No need to do that.  Instead, use the required phases from the same MCM.  0, 90, 180, 270, 2x, divide, ALL outputs may be used from the MCM....there is no restricyion to use a sungle port.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Highlighted
Explorer
Explorer
10,678 Views
Registered: ‎11-23-2013

Thanks for your answer.

 

I didn't explain my need clearly. In Xilinx's FPGAs, the MMCM's output clocks can be shifted and reconfigured dynamically.  When shift the output clocks, all the output clocks which enable the phase shift attribute will be shifted together.

But in my design, for example, I need two clocks clka and clkb which are synchronous. I want to shift clka and keep clkb unchanged sometimes, and sometimes shift clkb and keep clka.

 

The clock system above could be implemented by dynamically reconfigure the MMCM. I'm just afraid that we may need more such clocks more than one MMCM could generate, and all the clocks should be sync. So I try to use two MMCMs.

0 Kudos
Highlighted
Scholar
Scholar
18,383 Views
Registered: ‎02-27-2008

OK,

 

For the non-frequency modified outputs (CLK0), MMCM's driven by the same clock will be in sync.  The CLKDV, CLKFX, are not guaranteed to be in phase (as their state machines may have been reset at different times.

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

Highlighted
Explorer
Explorer
10,658 Views
Registered: ‎11-23-2013

 

Thank you!

 

Though I cannot get as many clocks I need, your answer is still very helpful.

0 Kudos