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Contributor
Contributor
2,580 Views
Registered: ‎04-03-2013

How to build up a frame grabber system?

hello,

i need help while building a fpga design. The designated target is to read in a parallel video stream and send it via ethernet in several pictures to pc (and display it on pc). Can anyone give me some hints how i should built up this system? To yet my intention is to use the vid_in_to_axi4s ip-core, a fifo ip core with what i can store the data into an external ram (maybe the axi virtual fifo controller?) and at last an ethernet ip-core (udp/ip - need to send ca. 70MByte/s). Is it recommended to build up the system like this? How can these ip-cores interact with each other? What ip-core for udp/ip is recommended?


thanks, mrb

 

 

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Historian
Historian
2,556 Views
Registered: ‎02-25-2008

Re: How to build up a frame grabber system?


@mrb wrote:

hello,

i need help while building a fpga design. The designated target is to read in a parallel video stream and send it via ethernet in several pictures to pc (and display it on pc). Can anyone give me some hints how i should built up this system? To yet my intention is to use the vid_in_to_axi4s ip-core, a fifo ip core with what i can store the data into an external ram (maybe the axi virtual fifo controller?) and at last an ethernet ip-core (udp/ip - need to send ca. 70MByte/s). Is it recommended to build up the system like this? How can these ip-cores interact with each other? What ip-core for udp/ip is recommended?


thanks, mrb



You should probably look up the AIA GigE Vision Standard.

 

And yes, what you want to do is a lot of work.

----------------------------Yes, I do this for a living.
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