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Adventurer
22,710 Views
Registered: ‎07-04-2013

## How to calculate Async Fifo Depth

Hi,

I want to calculate depth of an async fifo, but I am confused how to calculate it. The fifo parameters are as follows:

Write Clk Freq = 60 MHz.

Read Clk Freq = 100 MHz.

Maximum Write Burst Size = 1024.

Delay between writes in burst = 4 clk.

Read Delay = 2 clk.

Can anyone help with the formula for calculating the fifo depth.

Thanks in advance...!

16 Replies
Moderator
22,704 Views
Registered: ‎01-15-2008

## Re: How to calculate Async Fifo Depth

Scholar
22,698 Views
Registered: ‎02-27-2008

## Re: How to calculate Async Fifo Depth

k,

So every 5 60 MHz clocks you write?

And every 3 100 MHz clocks you read?

Write rate is 12 MHz (60/5)

Read rate is 33.3 MHz (100/3)

You are reading faster than you are writing...

Austin Lesea
Principal Engineer
Xilinx San Jose
Adventurer
22,679 Views
Registered: ‎07-04-2013

## Re: How to calculate Async Fifo Depth

Yes my read is faster than write, thats why I am confused how to calculate the depth.

So every 5 60 MHz clocks you write?

And every 3 100 MHz clocks you read?

Write rate is 12 MHz (60/5)

Read rate is 33.3 MHz (100/3)

How do u come up with the above conclusion.

My write burst is 1024 and delay between write burst is 4 Wr_clk.

Read delay is 2 Rd_clk.

Advisor
22,664 Views
Registered: ‎08-14-2007

## Re: How to calculate Async Fifo Depth

Hi,

your specifications are not very precise, which causes confusion.

Now for the writing it seems to be like this:

At a rate of 60 MHz you have a data burst of 1024 words and then a pause of 4 clock cycles.

Which means that you transfer 1024 words within 1028 clock cycles (Tcycle= 1/60MHz).

The reading part is still unclear.

Is it like Austin described:

1 read cycle and 2 pause cycles leading to 3*1024 cycles for 1024 data words

Which means a transfer rate of 1024 words within 3072 clock cycles (Tcycle= 1/00MHz).

Or do you have some (yet unmentioned)  burst reading here as well like this:

Reading 1024 words and then pause for 2 clock cycles ?

Which means a transfer rate of 1024 words within 1026 clock cycles (Tcycle= 1/00MHz).

You see there's a big difference.
Which will it be? Or will it be something completely different?

___________

Reading data faster than they are writen to the FIFO is no big problem.

That's what the Empty Flag is for. If the FIFO is empty, just stop reading.

(If there's no data, nothing needs to be processed)

Your fifo in such a configuration can be quite small, since you can empty it almost at once.

However, it depends on your algorithms and design architecture if this is a useful approach.

Writing faster than reading can also be handled, by checking the Full flag from the writing side.

Only that in most applications data sources are often reclessly spilling out their data, condemning the following hardware to be able to keep the pace.

So what is your application. Some background info can help to understand the problem.

Have a nice synthesis

Eilert

Adventurer
22,649 Views
Registered: ‎07-04-2013

## Re: How to calculate Async Fifo Depth

Hi Eilert,

The writing part is exactly same as you have mentioned. In the reading part, I read one word, the next clock is idle and on the next clock I read another word i.e. I read on every alternate clock.

Advisor
22,622 Views
Registered: ‎08-14-2007

## Re: How to calculate Async Fifo Depth

Hi,

so you have a datarate of 1024 words in 2048 clock cycles (Tcyc = 1/100MHz).

Now you can compare the read and write times for one block of data and check wether you are writing or reading faster.

According to that result you can see which Flag (empty/full) is more crucial for your data flow and decide which FIFO size works best for you. Other design properties might also have influence to this.

Have a nice synthesis

Eilert

Xilinx Employee
22,597 Views
Registered: ‎08-01-2008

## Re: How to calculate Async Fifo Depth

The effective depth will vary depending on the type of FIFO you generate.

For common clock FIFOs:

The depth you select is the actual depth you will receive in common clock case.

For independent clock FIFOs (Block Mem, Dist Mem type):

In the case of independent clocks, the physical depth of the FIFO you are receiving is actually the depth you have selected. However, the usable depth is always one less. At any given time, one location is not used in order to prevent the write_pointer and the read_pointer (internal pointers) from overlapping. If these two pointers were to overlap, you will not be able to determine if the FIFO is actually EMPTY or FULL. For this reason, the usable depth is always one less. You can think of FIFO as a circular buffer.

For FIFO16 (common of independent clocks):

In the built-in FIFO case, several FIFO16 primitives are cascaded together to form the desired depth. Since we need to account for the latency of the Full flag from each of these primitives, we are using ALMOSTFULL flags from each of these primitives for the generation of the FULL flag of the core. Therefore, with each of the primitives used, you will loose about 5 usable locations.

The last page of the FIFO Gen GUI is the summary page, and it will indicate the actual usable depth.

Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
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Adventurer
22,489 Views
Registered: ‎07-04-2013

## Re: How to calculate Async Fifo Depth

Hi!

Thank you all for your valuable suggessions.

Regards

Newbie
15,910 Views
Registered: ‎10-03-2015

## Re: How to calculate Async Fifo Depth

No of clock cycles to write 1024 words = 1024 clock cycles + Write delay = 1024 + 4 = 1028 clocks

Time duration of 1028 clocks in the time domain = 1028/(60*10^6) = 17.13 us

No of clocks in read domain which covers time duration of 17.13 us = 17.13 * 10^-6 * 100 * 10^6                                                                                            = 1713

No of clock cycles for reading a word = 1 + 3(Read delay) = 4 clocks

No of words read in 1713 clocks = 1713/4 = 428 words

Hence 1024 – 428 words must be buffered in the FIFO = 596 deep fifo is required.

Cook book equation, Depth = B – W *((F2)/(F1*R))

= 1024 – 1028*(100)/(60*4) = 596.

B = Write Burst = 1024

W = No of clocks for writing B = 1024 + Write Delay = 1024+4 = 1028

F2 = Read frequency

F1 = Write Frequency

R = No of clocks for reading Read Burst = 1+3 = 4 clocks // here read burst is 1 , so 1+4, if read burst was say 6, then R = 6+4 = 10

Thanks

Nizwan

Newbie
5,761 Views
Registered: ‎10-03-2015

## Re: How to calculate Async Fifo Depth

Sorry ! In the problem Read Delay was 2 clock cycles. But I took 3 clock cycles for the calculation

Voyager
5,521 Views
Registered: ‎04-02-2011

## Re: How to calculate Async Fifo Depth

Cook book equation, Depth = B – W *((F2)/(F1*R))

= 1024 – 1028*(100)/(60*4) = 596.

B = Write Burst = 1024

W = No of clocks for writing B = 1024 + Write Delay = 1024+4 = 1028

F2 = Read frequency

F1 = Write Frequency

R = No of clocks for reading Read Burst = 1+3 = 4 clocks // here read burst is 1 , so 1+4, if read burst was say 6, then R = 6+4 = 10

--------------------------------------------------------------------------------------------------------------------------------------------------------

even putting the correct # doesnt seems to get going....

Can you Justify the equation &&  ||  calculation ?

Newbie
4,158 Views
Registered: ‎07-12-2018

## Re: How to calculate Async Fifo Depth

man,you are a genius.Your simple explanation solves my puzzle easily.Thx

Newbie
4,137 Views
Registered: ‎07-25-2018

## Re: How to calculate Async Fifo Depth

 Assume that we have to design a FIFO with following requirements and We want to calculate minimum FIFO depth,
 Example: FIFO Depth Calculation A synchronized FIFO Writing clock 30MHz - F1 Reading clock 40MHz - F2 Writing Burst Size - B Case 1: There is 1 idle clock cycle for reading side - I Case 2: There is 10 idle clock cycle for reading side - I FIFO depth calculation = B - B *F2/(F1*I) If we have alternate read cycles i.e between two read cycle there is an IDLE cycle. FIFO depth calculation = B - B * F2/(F1*2) In our present problem FIFO depth = B - B *40/(30*2) = B(1-2/3) = B/3 That means if our Burst amount of data is 10, FIFO DEPTH = 10/3 = 3.333 = 4 (approximatly) If B = 20 FIFO depth = 20/3 = 6.6 = 7 or 8 (clocks are asynchronous) If B = 30 FIFO depth = 30/3 = 10 10+1 = 11 (clocks are asynchronous) If 10 IDLE cycles between two read cycles. FIFO DEPTH = B - B *F2/(F1*10) . = B(1-4/30) = B * 26 /30

Thanks & Regards,

Tom

Observer
4,061 Views
Registered: ‎05-14-2018

## Re: How to calculate Async Fifo Depth

The depth is not dependent on read and write clock.
For fifo depth you need to only calculate how many values you want to write into the fifo.
Observer
4,059 Views
Registered: ‎05-14-2018

## Re: How to calculate Async Fifo Depth

The fifo depth is independent of clock frequency of both read and write. Depth is calculated by how many values you want to write to fifo.

Explorer
3,927 Views
Registered: ‎06-25-2014

## Re: How to calculate Async Fifo Depth

Sorry, I'm a bit confused by all this..

If you are continuously writing 1024 gap=4, 1024 gap=4 etc.. @ 60Mhz then your effective data rate is 1024/1028*60Mz=59.77Mhz

On the read side you are taking one sample every other clock @ 100Mhz, so your read rate is 1/2*100Mhz= 50Mhz.

If this is correct then your FIFO is going to overflow no matter what depth you make it unless your gap is larger than 4, or you increase the read clock frequency.