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fllf2005
Visitor
Visitor
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Registered: ‎06-07-2017

How to change timing constraints in VDMA OOC.xdc files??

I am using Vivado 2016.4 for video application, my top timing constrains are different from OOC timing constrains. 

After synthesized, i got the warning below 

[Timing 38-316] Clock period '10.000' specified during out-of-context synthesis of instance 'design_1_i/axi_vdma_0' at clock pin 'm_axi_mm2s_aclk' is different from the actual clock period '5.000', this can lead to different synthesis results.

The design_1_axi_vdma_0_0_ooc.xdc is a read only file. I can not edit it in Vivado. Even I can modify it in other editor, but I can not re-synthesize the IP using the modified ooc.xdc file. 

 

I have searched in the forum, there is a similar issue, following is the link:

https://forums.xilinx.com/t5/General-Technical-Discussion/How-to-change-timing-constraints-in-OOC-xdc-files/td-p/752893

 

In this message, it provide a method to manually change the parameters, but this method does not work for VMDA. Because in properties of VMDA, there is no config for m_axi_mm2s_aclk.   

 

My question is, in the default OOC mode, how to override OOC constrains for each IP with my top constrains. Otherwise, I have to turn off OOC mode for synthesis.  

 

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josephsamson
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Registered: ‎10-05-2010

I don't think that changing the xdc file is the right approach. The block design validation step adjusts the xdc files to fix clock speeds and bus widths. 

 

Try this: 

1. close the block design.

2. open the block design

3. Right click in the Diagram window and select 'Validate Design'.

 

---

Joe

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