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Visitor
Posts: 11
Registered: ‎10-12-2009

How to checkpoint FPGA state?

Hi,

 

I believe it's possible to save the current state of an FPGA back to PC memory; however, I can't seem to find a description of how to use any of the ISE tools to do this.

 

Can anyone point me to directions of how to do this using Xilinx ISE 11.2 with a Virtex-5 device?

 

 

Thanks.

Moderator
Posts: 8,243
Registered: ‎02-27-2008

Re: How to checkpoint FPGA state?

rs,

 

http://www.xilinx.com/support/documentation/user_guides/ug360.pdf

 

page 129 describes how the capture, and restore features operate for Virtex 6.  Other technology FPGAs are similar in operation.

 

By capturing all of the IOB DFF values, and all of the CLB DFF values, all states stored in these memory resources may be read, stored somewhere else, and then placed back into the FPGA.

 

This does not capture the contents on Block RAM, nor SRL, so you logic design should not require these values to be kept in order to resume operation from where it was at the time the capture is performed.

 

One can go further, and read back the contents of the BRAM, and save those away, too.

 

One must stop to save the state, and then after restoring the state, one can restart (system clocks must stop during the capure and restore intervals).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
Posts: 11
Registered: ‎10-12-2009

Re: How to checkpoint FPGA state?

Thanks Austin.

 

I'm having difficulty issuing instructions through the JTAG interface. I believe this is done through issuing the instructions from the host PC to the FPGA; but, I haven't been able to find a satisfactory way of doing this.

 

Is there a library to use the JTAG interface for our Virtex-5 board? Do you know of any projects that have done similar things to use as a basis?

 

 

Thanks,

Rob.

Highlighted
Moderator
Posts: 8,243
Registered: ‎02-27-2008

Re: How to checkpoint FPGA state?

rs,

 

I am only familiar with our ISE Impact JTAG cable, and the software we provide.

 

http://www.xilinx.com/products/design_tools/logic_design/design_entry/impact.htm


Thru the Impact software, one can program the device, read the system monitor to determine the temperature, and the voltages, and perform a verify.


The verify step places the readback contents of the device into a file called impact.bin if the proper environment variables are set by the user (in Windows XP, these are 

set XIL_IMPACT_VIRTEX_DUMPBIN=1
set XIL_IMPACT_IGNORE_MASK_FILE=1

 

Parsing the readback file can be a bit arduous, as it is in binary format (I use a binary file editor that expresses the file in hex and binary), and we do not supply a map.  However, the .msk file (mask file) supplies information about where capture, and restore bits, and other dynamic content is located (so it may be ignored, as it changes).  Along with the 'diff' command (comapre two files, and express the differences, it isn't too hard to find initial conditions (by changing them in your design), and other bit locations of interest.

 

Sorry I can not be of more help,

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
Posts: 11
Registered: ‎10-12-2009

Re: How to checkpoint FPGA state?

Connecting your last two posts, I need to place the CAPTURE_VIRTEX6 primitive into my design (connecting the CLK to the CLK for my system).

 

 

What do I connect to the CAP input in the design?

 

The Verify operation does require the CAPTURE_VIRTEX6 primitve to be in my design?

 

 

Sorry for confusion on this issue. The documentation surrounding the page you point to contains sequences of shifting various words into the boundary scan register. I thought it was necessary to recreate this in a program of my own to perform the readback.

 

Thanks.

Moderator
Posts: 8,243
Registered: ‎02-27-2008

Re: How to checkpoint FPGA state?

rs,

 

The readback by Impact happens with or without the capture primitive.


As to what you "capture" as the last state (IO DFF, CLB DFF values), I am not familiar with how to trigger the capture (write) to the memory cells.


I suppose it needs a clock (everything is synchronous design), and it needs a strobe to tell it when to capture ...  perhaps someone else more familiar with the use of the primitive can chime in.

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
Posts: 11
Registered: ‎10-12-2009

Re: How to checkpoint FPGA state?

Should I place a post in another subforum?
Moderator
Posts: 8,243
Registered: ‎02-27-2008

Re: How to checkpoint FPGA state?

rs,

 

I read the use of the primitive, and you supply a clock, and a strobe (to cature).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
Visitor
Posts: 11
Registered: ‎10-12-2009

Re: How to checkpoint FPGA state?

I'm still working on adding the CAPTURE_VIRTEX5 primitive into my design. But, I'm still at a loss on how to actually perform the read back operation. The pdf instructions you pointed to earlier (pg. 120) seem to outline precisely what I need to do; however, I'm not clear on how to perform each of the steps (how does one "Clock five 1s on TMS..." with a Xilinx tool?).

 

 

Moderator
Posts: 8,243
Registered: ‎02-27-2008

Re: How to checkpoint FPGA state?

rs,

 

Use Impact, the programming tool, with a programming cable.

 

Select the "verify" operation (after re-reading how to set the environment variables.


Impact will then do everything for you, whether is be the JTAG port, or parallel or serial select map port.

 


The read back file will be called "impact.bin."  It will contain the entire bit map of the device: all CLB columns, BRAM columns, capture bits, everything.

 

To find the capture bits, use a file compare with a readback before a capture, and one after a capture.

 

Austin Lesea
Principal Engineer
Xilinx San Jose