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Visitor dbabayev
Visitor
919 Views
Registered: ‎03-01-2010

How to continue running FPGA when external clock fails?

Customer is supplying external clock to run system FPGA. If clock fails need to place system into safe mode. Any ideas on how to continue running FPGA when external clock fails?

 

Greatly appreciate any advice.

Thanks!

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3 Replies
Contributor
Contributor
912 Views
Registered: ‎09-01-2015

Re: How to continue running FPGA when external clock fails?

Usually systems that have this sort of requirement get a pending clock failure indicator and have a limited time to "go into safe mode".

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Scholar jmcclusk
Scholar
902 Views
Registered: ‎02-24-2014

Re: How to continue running FPGA when external clock fails?

The STARTUPE2 block has a CFGCLOCK output.   It's not super stable, or precise... but it's a workable clock you can use as a fallback to do some basics.   I'm assuming your FPGA is a series 7 or later device.     You can use it to run a clock detection circuit, and switch your clock tree to the CFGCLOCK if needed.

Don't forget to close a thread when possible by accepting a post as a solution.
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Scholar pedro_uno
Scholar
859 Views
Registered: ‎02-12-2013

Re: How to continue running FPGA when external clock fails?

Another approach is to add a local reference clock to the board. Optical communications equipment is nearly always designed to have a holdover mechanism that kicks in if the external reference clock disappears. The master PLL can failover to the local reference. I wonder if this is possible with Xilinx PLL's.
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DSP in hardware and software
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