03-26-2018 11:31 AM
Customer is supplying external clock to run system FPGA. If clock fails need to place system into safe mode. Any ideas on how to continue running FPGA when external clock fails?
Greatly appreciate any advice.
03-26-2018 11:38 AM
Usually systems that have this sort of requirement get a pending clock failure indicator and have a limited time to "go into safe mode".
03-26-2018 11:54 AM
The STARTUPE2 block has a CFGCLOCK output. It's not super stable, or precise... but it's a workable clock you can use as a fallback to do some basics. I'm assuming your FPGA is a series 7 or later device. You can use it to run a clock detection circuit, and switch your clock tree to the CFGCLOCK if needed.
03-26-2018 02:35 PM