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Anonymous
Not applicable
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How to debug AXI Video IN overflow pin?

Hi, I have been trying to debug my system and need to know if overflow happens in the AXI Video In IP. I tried probing the pin both ways, but so far - unsuccessfully:

 

1. I concatinated this pin with the interrupt pins from the VDMA and connected to the IRQ_F2P pin of the Zynq. However, the generated xparameters.h file contains only interrupt definitions for the VDMA (61, 62), and no definition present for the overflow pin (I expected to be 63). Is it because the overflow pin is the flag and not the interrupt pin? Does that matter?

 

2. I marked this overflow pin (unconnected) for debug. No other nets were marked for debug. After implementation, I set up the ILA to trigger on the rising edge of this overflow signal, and try to arm the trigger by pressing > button. The console says that the trigger was armed, but the trigger status never goes to the "waiting for trigger" state. Again, what's wrong with my setup?

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

 
1. I concatinated this pin with the interrupt pins from the VDMA and connected to the IRQ_F2P pin of
the Zynq. However, the generated xparameters.h file contains only interrupt definitions for the VDMA
(61, 62), and no definition present for the overflow pin (I expected to be 63). Is it because the
overflow pin is the flag and not the interrupt pin? Does that matter?

I would think it would work fine with this setup. Make sure to 'Regenerate BSP sources' in SDK after you've made this change. If this doesn't work, can you share xparameters.h and a screenshot of your BD?

 

2. I marked this overflow pin (unconnected) for debug. No other nets were marked for debug. After
implementation, I set up the ILA to trigger on the rising edge of this overflow signal, and try to
arm the trigger by pressing > button. The console says that the trigger was armed, but the trigger
status never goes to the "waiting for trigger" state. Again, what's wrong with my setup?

What's your video resolution/pixel clock? I see this when working with low resolution video. The reason is that the pixel clock is usually pretty low (like ~25MHz for VGA). The ILA has a requirement that the JTAG frequency must be <2x the ILA clock frequency (I think that's the requirement, off the top of my head...). In this case, simple solution is to lower the jtag clock frequency when connecting via the vivado debugger.

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Anonymous
Not applicable
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@bwiec I will try to export the new bsp. Maybe I missed something. As for the SDK - I always delete and create a new project - so did not need to regenerate the BSD.

 

I indeed run the 25.2MHz VGA video. How do I alter the JTAG clock?

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bwiec
Xilinx Employee
Xilinx Employee
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Registered: ‎08-02-2011

Oh okay, that's probably not the problem then.

 

In vivado, when you open the hardware manager and connect to target (DON'T let it auto-connect), one of the options is the jtag clock frequency. Let me know if you can't find it and I'll grab a screenshot.

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Anonymous
Not applicable
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@bwiec Ok, after I changed the clock frequency from 15MHz to 10MHz, I was able to arm the trigger on the overflow pin and debug it. Just for clarification for this example, the ILA clock is the same clock as aclk clock on the Video in block?

 

I tried to re-create the sdk project but the interrupt for the overflow pin in still not to be found in the xparameters.h file. Any ideas why this happens?

 

intr.PNG
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