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Explorer
Explorer
7,210 Views
Registered: ‎06-28-2008

How to decrease the delay of combinational logic ??

input [1:0] ce;

input oe1;

input oe0;

 

inout data_bus;

 

wire a1;

wire a2;

wire a3;

 

assign a1 = (!ce[1]) & oe1;

assign a2 = (!ce[0]) & oe0;

assign a3 = a1 | a2;

 

 

assign data_bus = a3 ? dout : 32'bzzz...;

 

dout is register output which are driven by internal clock.

I use chipscope to watch these signals.

dout is right ,but the timing of  data_bus is uncertain.---Sometimes early,sometimes late.

 

I guess that the delay of the combinational logic of a3  is uncertain.

So the timing of databus is uncertain.

 

How can I solve the problem ???

How to decrease the delay of combinational logic ??

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13 Replies
Teacher eteam00
Teacher
7,203 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

the timing of  data_bus is uncertain.---Sometimes early,sometimes late.

 

early or late is a relative term.  early or late referenced to... what?

 

How do you measure output delay?

  • internal clock edge to data_bus output?
  • ce/oe input to data_bus output?

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
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2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
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5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
7,199 Views
Registered: ‎06-28-2008

Re: How to decrease the delay of combinational logic ??

The timing is fixed   which is configured in DSP and determined by DSP.

(fixed read and write latency)

 

I can not measure the delay.

 

But DSP can receive the data,so it is judged by DSP.

 

Sometimes the first data is wrong,othertimes the last data is wrong.

All other data are right.

 

So I guess the issue is the uncertain delay.

 

 

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Teacher eteam00
Teacher
7,183 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

Suggest you solicit the assistance of an experienced hardware design engineer to help you understand and express (describe) your problem.  You cannot solve or define a timing problem without a timing reference.

 

If you are describing an asynchronous (to the FPGA) register read by an external processor, you should 'freeze' the register value being read by the DSP.  Use one of the OE or CE inputs from the processor as a "freeze" signal.  There are a number of ways to implement this in hardware, and consideration must be given to the processor read cycle timing and the FPGA's internal clock frequency.

 

For example:

 

  • Use internal FPGA clock to synchronise CE input.
  • Use synchronised CE input (when de-asserted) as clock enable to a register sampling (and freezing)  the dout register
  • The sampled copy of dout is synchronised to both the internal FPGA clock and the DSP read cycle
  • Use the sampled copy of dout as input to the data_bus output buffers.

Depending on the FPGA internal clock frequency and the DSP bus timing, the example described above may not work at all.  Without knowing these important details, it is impossible to be certain.

 

In other words, what you describe as a combinatorial delay problem is very likely two clock domain crossing problems:

  • processor to FPGA
  • FPGA to processor

Does this address the problem you have in mind?  Does this make sense, or would additional explanation be helpful?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
7,173 Views
Registered: ‎06-28-2008

Re: How to decrease the delay of combinational logic ??

Hi,Bob.  I know your meaning about reference.

 

Please look at the timing graph.

 

 

I use AECLKOUT given by DSP as the clock of my data_output interface module.

 

Now  ACE,AOE,AEA are not synchronized by AECLKOUT.

 

 I use chipscope to watch the data.

 

My local dout is driven by AECLKOUT. It is correct in chipscope.

 

Because ILA core is driven by AECLKOUT,and my databus AED is driven by a switch signal a3 which is generated by combinational logic.

So in chipscope  AED is "wrong" due to the sample time.

In DSP,AED is correct but sometimes early,other times late.

 

 

emif.jpg
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Teacher eteam00
Teacher
7,168 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

Is this circuit board already designed, or is this still (at this point) a paper design?

 

Later tonight I can put together a coherent followup, but this question is useful information.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Teacher eteam00
Teacher
7,140 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

I have not heard back from you on the question of the board design status.  Therefore, I will not dwell on fine design details.

 

In general, your design application is a classic example of a source-synchronous interface design.

 

You need to distribute the 100MHz clock AECLKOUT to all of the bus IO pins, with essentially zero delay.  To do this, you can use either a DCM or a PLL to regenerate the 100MHz clock, use a BUFG to distribute the regenerated clock throughout the FPGA, and use a BUFIO2FB to phase-align the regenerated clock to the AECLKOUT input.  There are numerous examples (and diagrams) of how to do this in UG382.

 

The 100MHz interface clock frequency is well within the capabilities of the Spartan-6 device, and there is no need for using ISERDES or OSERDES blocks (or IDDR and ODDR) to support 100Mbit/sec bandwidths.  For skew control, however, you should register both inputs and outputs (and output enables) at the IOBs.

 

Using this approach, interface between the FPGA and the TI processor is straightforward.  The next design hurdle is the alignment between the internal FPGA system clock and the 100MHz interface clock.  Without any details of the internal logic and clock, offering useful implementation advice would be premature.

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
7,132 Views
Registered: ‎06-28-2008

Re: How to decrease the delay of combinational logic ??

Thank you,Bob.

 

I will have a try.

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Teacher eteam00
Teacher
7,129 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

Don't forget to post the answers to the following questions:

 

1.  Is the circuit board (and FPGA pinout) already designed and built?  Or is this the circuit board design still 'flexible'?

 

2.  What is the internal FPGA 'system' clock frequency?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
7,111 Views
Registered: ‎06-28-2008

Re: How to decrease the delay of combinational logic ??

Don't forget to post the answers to the following questions:

 

1.  Is the circuit board (and FPGA pinout) already designed and built?  Or is this the circuit board design still 'flexible'?

 

It has been designed and now we are debugging it.

 

2.  What is the internal FPGA 'system' clock frequency?

 

The internal FPGA 'system' clock is also 100M.

 

Now we use FIFO, the data driven by internal FPGA 'system' clock are written to FIFO, and the CE and OE by DSP are used to read FIFO. So I think there is no Clock Domain Cross problem.

 

The data read from FIFO have been synchronized by AECLKOUT .But the a3 signal  are not synchronized now .So I will change the design according to your advice.

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Teacher eteam00
Teacher
3,761 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

The data read from FIFO have been synchronized by AECLKOUT .But the a3 signal  are not synchronized now .So I will change the design according to your advice.

 

What is the "a3" signal?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
3,758 Views
Registered: ‎06-28-2008

Re: How to decrease the delay of combinational logic ??

input [1:0] ce;

input oe1;

input oe0;

 

inout data_bus;

 

wire a1;

wire a2;

wire a3;

 

assign a1 = (!ce[1]) & oe1;

assign a2 = (!ce[0]) & oe0;

assign a3 = a1 | a2;

 

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Teacher eteam00
Teacher
3,755 Views
Registered: ‎07-21-2009

Re: How to decrease the delay of combinational logic ??

assign a1 = (!ce[1]) & oe1;

assign a2 = (!ce[0]) & oe0;

assign a3 = a1 | a2;

 

Each oe signal is asserted HIGH (1 = enable output)

Each ce signal is asserted LOW (0 = chip enabled)

 

Is this correct?

 

And signal a3 must be delayed by 2(?) AECLK cycles to enable the data_bus output?

 

-- Bob Elkind

SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide. Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts. If I write a good post, then I have been good for nothing.
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Explorer
Explorer
3,747 Views
Registered: ‎06-28-2008

Re: How to decrease the delay of combinational logic ??

assign a1 = (!ce[1]) & (!oe);  // choose internal output1

 assign a2 = (!ce[0]) & ccc;   // choose internal output2

 assign a3 = a1 | a2;

 

oe = 0 is valid ,ccc is another signal,I made a mistake .

 

 

To delay 2 AECLK is not important if  the read latency of DSP is configured big enough.

So I can change the code to  use clock to generate a1 ,a2 and a3.

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