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Observer
Observer
2,422 Views
Registered: ‎12-16-2011

How to use dat / txt file in testbench...

I'm a new and clumsy VHDL user but wish to accept a data file outside VHDL and then read it and test it under testbench.

 

Could someone point me to a useable example of this sort of thing?

Any pointers?

thanks,
Indraneel

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Teacher
Teacher
2,421 Views
Registered: ‎09-09-2010

You need to use the standard 'textio' package (and possibly the 'std_logic_textio' package) to open and read the file.

Enter "vhdl textio tutorial" into any good Internet search engine for useful information on how to use them...

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"If it don't work in simulation, it won't work on the board."
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