Dear all,
I fairly new to fpgas and for learning porpuses I am developing a I2C Module in VHDL.
I am having trouble with the i2c clock because it is not in phase with a signal that I created and I don't know why.
I will put the code in here as well as a screenshot of the ISim wave in hope that someone could give a hint on what I am doing wrong. I know that the module is not ready..
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
i2c_sda : out STD_LOGIC;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
constant IDLE : std_logic_vector :="000";
constant START : std_logic_vector :="001";
constant ADDRESS : std_logic_vector :="010";
constant RW : std_logic_vector :="011";
constant ACK : std_logic_vector :="100";
constant DATA : std_logic_vector :="101";
constant ACK2 : std_logic_vector :="110";
constant STOP : std_logic_vector :="111";
signal addr: std_logic_vector (6 downto 0) := (others => '0');
signal dat: std_logic_vector (6 downto 0) := (others => '0');
signal i2c_scl_signal: std_logic;
signal state: std_logic_vector (2 downto 0);
begin
I2C: Process(clk)
variable Counter : integer range 0 to 7;
begin
if falling_edge(clk) then
if reset = '1' then
i2c_scl_signal <= '1';
elsif state = IDLE or state = START or state = STOP then
i2c_scl_signal <= '1';
else
i2c_scl_signal <= not i2c_scl_signal;
i2c_scl <= i2c_scl_signal;
end if;
end if;
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
i2c_sda <= '1';
i2c_scl <= '1';
addr <= "0110000";
dat <= "0011100";
Counter := 0;
end if;
case state is
when IDLE =>
i2c_sda <= '1';
state <= START;
when START =>
i2c_sda <= '0';
state <= ADDRESS;
Counter := 6;
when ADDRESS =>
i2c_sda <= addr(Counter);
if Counter = 0 then state <= RW;
else Counter := Counter -1;
end if;
when RW =>
i2c_sda <= '1';
state <= ACK;
when ACK =>
state <= DATA;
Counter := 7;
when DATA =>
i2c_sda <= dat(Counter);
if Counter = 0 then state <= ACK2;
else Counter := Counter - 1;
end if;
when ACK2 =>
state <= STOP;
when STOP =>
i2c_sda <= '1';
state <= IDLE;
when others => state <= IDLE;
end case;
end if;
end Process I2C;
end Behavioral;
To be more specific, when I enter in the Address state, at the falling edge of the clock, both i2c_scl and i2c_scl_signal should go from 1 to 0 (where the yellow mark is) but the signal does that and the i2c_scl doesn't. This last wave waits one period to go from 1 to 0..why? I put some of the code in bold to be easier for you to track the problem.
Thank you in advance for your help!
Hello again :) ,
I'm trying not to bore you too much but I need your help again.
I am trying to push this to a new level and implement the i2c module in a really i2c IC. I look around and I found a TMP421 resting so I decided to try reading it. http://www.ti.com/lit/ds/sbos398c/sbos398c.pdf
As I don't have a logic analyzer avaiable, I'm trying to use chipscope to read the values from the sensor.
Below, the current vhdl code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:45:53 03/09/2014
-- Design Name:
-- Module Name: i2c - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity i2c is
Port ( CLK_27MHz : in STD_LOGIC;
reset : in STD_LOGIC;
i2c_sda : inout STD_LOGIC;
i2c_scl : out STD_LOGIC);
end i2c;
architecture Behavioral of i2c is
constant IDLE : std_logic_vector :="0000";
constant START : std_logic_vector :="0001";
constant ADDRESS : std_logic_vector :="0010";
constant RW : std_logic_vector :="0011";
constant ACK : std_logic_vector :="0100";
constant DATA : std_logic_vector :="0101";
constant ACK2 : std_logic_vector :="0110";
constant DATA2 : std_logic_vector :="0111";
constant NACK : std_logic_vector :="1000";
constant STOP : std_logic_vector :="1001";
signal clk: std_logic := '0';
signal Counter: std_logic_vector (6 downto 0);
signal addr: std_logic_vector (6 downto 0) := (others => '0');
signal dat: std_logic_vector (6 downto 0) := (others => '0');
signal dat2: std_logic_vector (6 downto 0) := (others => '0');
signal i2c_scl_signal: std_logic;
signal state: std_logic_vector (3 downto 0);
begin
Prescaler: process (CLK_27MHz)
begin
if rising_edge(CLK_27MHz) then
if Counter < "1000011" then
Counter <= Counter + 1;
else
clk<=not clk;
Counter <= (others=>'0');
end if;
end if;
end process Prescaler;
I2C: Process(clk)
variable Counter : integer range 0 to 7;
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
i2c_sda <= '1';
i2c_scl <= '1';
addr <= "1001100";
-- dat <= "0001010";
Counter := 0;
elsif state = IDLE or state = START or state = STOP then
i2c_scl_signal <= '1';
else
i2c_scl_signal <= not i2c_scl_signal;
i2c_scl <= not i2c_scl_signal;
end if;
case state is
when IDLE =>
i2c_sda <= '1';
state <= START;
when START =>
i2c_sda <= '0';
state <= ADDRESS;
Counter := 6;
when ADDRESS =>
i2c_sda <= addr(Counter);
if Counter = 0 then state <= RW;
else Counter := Counter -1;
end if;
when RW =>
i2c_sda <= '1';
state <= ACK;
when ACK =>
if i2c_sda = '0' then
state <= DATA;
Counter := 6;
end if;
when DATA =>
dat(Counter)<=i2c_sda;
if Counter = 0 then state <= ACK2;
else Counter := Counter - 1;
end if;
when ACK2 =>
if i2c_sda = '0' then
state <= DATA2;
Counter := 6;
end if;
when DATA2 =>
dat2(Counter)<=i2c_sda;
if Counter = 0 then state <= NACK;
else Counter := Counter - 1;
end if;
when NACK =>
i2c_sda <= '1';
state <= STOP;
when STOP =>
i2c_sda <= '1';
state <= IDLE;
when others => state <= IDLE;
end case;
end if;
end Process I2C;
end Behavioral;
The problem is...I can't read anything...The SDA line doesn't send or reads any addresses.. There are the waveforms that I get:
when I press the reset button, the SDA gets strange, why??
I don't have a logic analyzer avaiable but I used my digital osciloscope and I get similar results from the ones you can see above.
What I am doing wrong?
@bassman59 wrote:
Two things:
a) Without seeing a test bench and a model of the I2C slave, we can't guess at why it doesn't work.
b) Stop using std_logic_vectors to count. Use a natural.
a) Are you asking for these???
b) I'll look into it. Thank you for the tip.