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Adventurer
Adventurer
15,816 Views
Registered: ‎08-04-2014

I2c code in verilog

Hi,

 

I want write I2c code for 24 bit register address and 32 bit data width in verilog ,can any one help  me?

 

 

Thanks

Sunitha

 

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15 Replies
Instructor
Instructor
15,768 Views
Registered: ‎08-14-2007

Re: I2c code in verilog

What are you trying to do with this code?  Do you need master code to connect with an external slave device?  Or do you have an external master and want the FPGA to be the slave device?

 

I2C is a byte-oriented protocol.  There are different ways to handle wider register address, but it is unusual to have wider data.  Do you have a specification for the external device you will be communicating with?

-- Gabor
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Adventurer
Adventurer
15,717 Views
Registered: ‎08-04-2014

Re: I2c code in verilog

Thanks for reply,

 

Yes i am connecting SRIO switch with FPGA.Switch has internal registers with 24 bit register address and 32 bit data.

And FPGA will acts as Master and Switch  will act as slave mode.

 

So to write those registers i want I2c master code for 24 bit register address and 32 bit data,Can please help me?

 

Regards

Sunitha

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Instructor
Instructor
15,707 Views
Registered: ‎08-14-2007

Re: I2c code in verilog

It would help to have the data sheet for the SRIO switch you're using.  The I2C bus defines a byte-based transfer mechanism with either 7 or 10 bit slave addressing.  Most IC's use a 7-bit slave address for the device.  Internal addressing ("register address") is handled as a simple write, where the first byte after the device address starts the internal address.  For more than 8-bit internal addressing, you would send more address bytes, followed by data to write.  In order to read, you would only send the internal address bytes, then start a read operation, either by issuing a stop followed by a start or using a "repeated start."  Most I2C slaves respond to either mechanism, but I have seen some, notably chips from Analog Devices, which require the repeated start for reads.

 

As a starting point I have attached a simple I2C master for accessing registers in slaves using a 7-bit device address, 8-bit internal register address, and 8-bit register data.  You could extend this to 24-bit addressing and 32-bit data by adding additional bytes.  Note that you can't just make the "bytes" 24 or 32 bits.  Each byte is followed by an acknowledge cycle and needs to be transmitted independently.  You'll need to look at the data sheet for your device to determine the correct byte order for data or address larger than 8 bits (i.e. LSB first or MSB first).

-- Gabor
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Adventurer
Adventurer
15,597 Views
Registered: ‎08-04-2014

Re: I2c code in verilog

HI

Thanks for your reply,

 

Did u work in this code?

Actually i have written Test bench with

sys_clock=100Mhz 

active low Reset

wr_ctrl=1

 

But even state is also not changing,It is running only one iteration of timer(330 to 0).did i miss anything in testbench?

 

Thanks

Sunitha

 

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Instructor
Instructor
15,570 Views
Registered: ‎08-14-2007

Re: I2c code in verilog

Since you didn't post your test bench it's hard to say what you might have missed.  Here's a simple one with no slave attached that shows what happens when you start up, and then attempts a write.  The status at the end will show 6000 hex indicating that there was no acknowledge pulse from the slave on either the address or data cycles.

-- Gabor
I2C_Master.PNG
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Adventurer
Adventurer
15,526 Views
Registered: ‎08-04-2014

Re: I2c code in verilog

Hi,

Thanks for your reply,

 

If i want change ctrl_data with

7 bit slave address

24 bit register address

32 bit data width 

 

whare i have to modify in this code?can you please tell me,its urgent require for me

 

Regards

sunitha

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Adventurer
Adventurer
15,484 Views
Registered: ‎08-04-2014

Re: I2c code in verilog

Hi,

Thanks for your reply,

 

If i want change ctrl_data with

7 bit slave address

24 bit register address

32 bit data width 

 

whare i have to modify in this code?can you please tell me,its urgent require for me

 

Regards

sunitha

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Newbie arun@12
Newbie
4,332 Views
Registered: ‎07-06-2018

Re: I2c code in verilog

 

 

Hi,

 

I want write I2c code in verilog ,can any one help  me?

 

 

Thanks,

Arun .

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Newbie nadhimer
Newbie
2,848 Views
Registered: ‎10-31-2018

Re: I2c code in verilog

i dont know what is happening, I barely understand i2c and vhdl, and i dont know what to do. Your video is the best one I have found untill now, thank you.
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Newbie pruthvi@007
Newbie
2,005 Views
Registered: ‎12-04-2018

Re: I2c code in verilog

can you please share the specification document.

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Instructor
Instructor
1,972 Views
Registered: ‎08-14-2007

Re: I2c code in verilog

The I2C specification is available here

-- Gabor
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Newbie pruthvi@007
Newbie
1,740 Views
Registered: ‎12-04-2018

Re: I2c code in verilog

can you please share the i2c slave code.

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Instructor
Instructor
1,666 Views
Registered: ‎08-14-2007

Re: I2c code in verilog

I shared the code some time ago in this thread.  It's attached to the post.

-- Gabor
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Newbie pruthvi@007
Newbie
1,523 Views
Registered: ‎12-04-2018

Re: I2c code in verilog

can you please share the testbench in which both slave and master should be attached. I was trying second data transfer format as per below mentioned it is not working.

Possible data transfer formats are:
• Master-transmitter transmits to slave-receiver. The transfer direction is not changed
(see Figure 11). The slave receiver acknowledges each byte.
• Master reads slave immediately after first byte (see Figure 12). At the moment of the
first acknowledge, the master-transmitter becomes a master-receiver and the
slave-receiver becomes a slave-transmitter. This first acknowledge is still generated
by the slave. The master generates subsequent acknowledges. The STOP condition
is generated by the master, which sends a not-acknowledge (A) just before the STOP
condition.
• Combined format (see Figure 13). During a change of direction within a transfer, the
START condition and the slave address are both repeated, but with the R/W bit
reversed. If a master-receiver sends a repeated START condition, it sends a
not-acknowledge (A) just before the repeated START condition

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Newbie pruthvi@007
Newbie
1,438 Views
Registered: ‎12-04-2018

Re: I2c code in verilog

can anyone explain me why the below lines are used in i2c_master code?

 

  if (ctrl_reg[31])   // reading requires subaddr write then data read
                if (wr_cyc)
                  shift_reg <= {ctrl_reg[23:17],1'b0,1'b1,ctrl_reg[15:8],1'b1,ctrl_reg[30],7'b0,1'b0};
                else
                  shift_reg <= {ctrl_reg[23:17],1'b1,1'b1,8'hff,1'b1,8'b0,1'b0};

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