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Explorer
Explorer
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Registered: ‎10-27-2013

IO pins when using Single Chip Cryptography (SCC)

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When you use isolated design flow(IDF) for SCC  Is the FPGA pin locked to isolated region

ie

while implementing the hardware design do i  need to ensure that the FPGA pins I choose for external interfaces fall in the isolated region intended. 

 

Usually our design follow  has been to implement the hardware and then do the RTL development and pin assignment based on Schematics.

 

Does IDF uses a different flow?? After identifying the Isolated regions assign the accessible FPGA pins to appropriate external devices.

 

 

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Scholar
Scholar
1,245 Views
Registered: ‎02-27-2008

Yes,

 

It is always best to floorplan your IO and logic, but be prepared to have to change it (in this case because IDF indicates there is insufficient separation, or an IO pin is not where you need it to be).  You cannot floorplan logic until you have RTL written.  If needed, write a wrapper for the logic required with all inputs and outputs, with a simple set of registers inside (no actual logic).  This then can be floorplanned.  In its simplest form, you can have a red_block_wrapper, and a black_block_wrapper, and apply the IDF to check red is isolated from black.  The logic doesn't matter here, as what is being verified is there is no possibility of a single bit flip AND an intrinsic fault to create a path not intended between the blocks so isolated.

 

So, the process (flow) is not linear, you will go back and forth a few times to resolve all your issues along with your physical pcb needs.

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post

1 Reply
Highlighted
Scholar
Scholar
1,246 Views
Registered: ‎02-27-2008

Yes,

 

It is always best to floorplan your IO and logic, but be prepared to have to change it (in this case because IDF indicates there is insufficient separation, or an IO pin is not where you need it to be).  You cannot floorplan logic until you have RTL written.  If needed, write a wrapper for the logic required with all inputs and outputs, with a simple set of registers inside (no actual logic).  This then can be floorplanned.  In its simplest form, you can have a red_block_wrapper, and a black_block_wrapper, and apply the IDF to check red is isolated from black.  The logic doesn't matter here, as what is being verified is there is no possibility of a single bit flip AND an intrinsic fault to create a path not intended between the blocks so isolated.

 

So, the process (flow) is not linear, you will go back and forth a few times to resolve all your issues along with your physical pcb needs.

Austin Lesea
Principal Engineer
Xilinx San Jose

View solution in original post