UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Observer rahul_0308
Observer
129 Views
Registered: ‎05-08-2018

ISLA214P50 ADC chip interfacing with zynq FPGA

Hi,

I am interfacing ADC with FPGA which runs at 500 MSPS.

For the same bit file, performance is varying from on/off conditions.

Adc data is fixed to one static value and which is same for all on conditions when it is not coming.

Timing constraints are applied at UCF.

Please let me know possible reasons.

Thanks in advance.

0 Kudos