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ameypatil28
Observer
Observer
7,886 Views
Registered: ‎11-16-2011

Image processing stuff

Hello!!

 

I m a student .Want to make a project on virtex 5 mainly XC5LX110T.

 

My job is to read image file and then the contents of image like RED GREEN AND BLUE values of image to be loaded in block rams of virtex 5 fpga kit and another block ram for storing another variable tmeperature of size same as R G B arrays. 

 

Xilinx have mentioned that XC5LX110T has internal RAM memory of 5328Kb so what size of image will I have to use to ensure that I use internal DDR RAM.

 

And how to load all values of RGB in the block ram???

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10 Replies
eteam00
Instructor
Instructor
7,885 Views
Registered: ‎07-21-2009

You are basically asking how to design what you have described, is this correct?

 

What experience with FPGA design do you have?

 

Your first step is to define the requirements of your design, including the size of the image you wish to store.  Do you have such a design definition?

 

Your next step is to transform your design definition to a block diagram.  Do you have a block diagram for your new design?

 

Then you need to describe each block in your design with more detail -- enough detail to clearly describe your Verilog or VHDL implementation code.

 

Finally, you translate the detailed design description, block by clock, into HDL code.

 

-- Bob Elkind

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rcingham
Teacher
Teacher
7,883 Views
Registered: ‎09-09-2010

The internal RAM of Virtex-5 is not DDR.

The maximum size of image you can store internal to the FPGA will depend on how many bits/pixel you need, but will be rather small:
196 * 18Kb gives 48 * 18Kb per store,
and if you need 24 bits/pixel, because of the memory organisation, that will give 24k pixels/image.

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"If it don't work in simulation, it won't work on the board."
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ameypatil28
Observer
Observer
7,878 Views
Registered: ‎11-16-2011

My image is 24bits/pixel i.e colour image .

 

I want to store each element of image i.e R G and B colour values in internal RAM.

 

So in all I need four block ram (one extra for storing Temp array) of size say 100 by 100  pixels

 

whats d way i do it?????

 

Thanks

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rcingham
Teacher
Teacher
7,872 Views
Registered: ‎09-09-2010

Where are you reading this image from?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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ameypatil28
Observer
Observer
7,858 Views
Registered: ‎11-16-2011

Thanks alot for reply....


I am trying to read image from my computer harddrive.


Say i have image in c: drive this image i have to read into block rams of virtex 5 fpga
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rcingham
Teacher
Teacher
7,842 Views
Registered: ‎09-09-2010

"Say I have image in C: drive and it is this image I want to write into BlockRAMs of the Virtex-5 FPGA."

You will need some software running on the PC that sends the file via a communication channel to the board with the FPGA on.
There will need to be complementary firmware in the FPGA to receive the image data from the communication channel, and write it into the desired area of BlockRAM. A lot of learing for you to do!

What board do you have?

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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ameypatil28
Observer
Observer
7,827 Views
Registered: ‎11-16-2011

I am having ML505 and it is having serial and USB both interface.
I m thinking of using serial interface .
Means inputting image in the form of hex codes from @PC to @ML505 serial buffer.
Then i will write a code in hdl which will continuosly monitor the SBUFF when any data comes then serially put it to block RAM.
Then i will start my algo for calculating result .
This result should be send by wrting sum UART transmit module in hdl to send that result back to @pc.
I am having image of 24 bit .
It is colour image thats why 24 bit.
I want to play with all 24 bits of image.
Please guide me on this.
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rcingham
Teacher
Teacher
7,826 Views
Registered: ‎09-09-2010

"Please guide me on this."

Design and test is small stages.

Do an LED-blinking design FIRST OF ALL to get confidence with the tools. Then proceed with your design in stages.
For instance, get the PC -> FPGA communications up next.
Does the PC need some return value back from the FPGA to indicate that the FPGA has received data?
How does the FPGA know when it has got all the data it needs?


------------------------------------------
"If it don't work in simulation, it won't work on the board."
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ameypatil28
Observer
Observer
7,821 Views
Registered: ‎11-16-2011

Yes when FPGA get total image **bleep** text file then after receiving complete file it should compute the result.
I will know that computations happened coz i will be setting the image size constraints so i know how many HEX bytes will be der in text file.
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ameypatil28
Observer
Observer
1,948 Views
Registered: ‎11-16-2011

Now doing further study I got to know that I should always put count or size of image at the start of image text file.This count will be in hex code.So once I get hex byte of size I will set counter for the same value.and using counter value I will do all the computation.
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