09-12-2011 06:06 PM
I'm trying to implement delay chain in Virtex-6 with the granularity of ~100ps. I'm thinking of using CARRY4 and MUXCY_L to implement it.
What are the P&R constraint that I need to include to avoid large routing delay and how can I tightly control the delay which doesn't change from run to run and have better VT control also.
I'll aprreciate any suggestions including other ways of implementing delay chain.
09-12-2011 10:42 PM
I think we don't need to discuss the problems that arise rom using combinatorical delay chains.
And you probably know about the programmable delays in the IOBs of actual FPGAs.
You could instantiate the primitives and add lots of timing and placement constraints to the UCF file to keep timing in controll just a little bit.
But there may be a more conveniant solution. (I haven't tried it, just came to my mind when reading about your problem)
Create a simple N-bit adder with Carry_in
sum <= a+b+ci;
and have the adder inputs set to maximum (e.g. 255 for 8 bit) and zero constantly.
So yo actually have something like this (again for 8 bit):
sum <= "11111111"+"00000000"+ci;
If you feed some signal to ci of this adder, it will ripple through the carry chain.
The big advantage is that ISE knows how to buld adders fast an with a controlled placement.
Normally you get a column of slices with a well defined routing.
Maybe you need to care a little about optimization (e.g using KEEP constraints).
Also it should be possible to make the design "tapable" by connecting to each carry out of the adder chain.
Hope this is helpfull. Please keep in mind that only a post-par timing simulation can show you the true behavior of such a system.
Have a nice synthesis
09-13-2011 10:35 AM
It sounds good to me. I also need to tap the delay after every adder so would be needing MUXes. Is there any way to choose MUXCY* (i guess it is the fastest mux) to be placed in column next to carry chain column so that there is minimum routing delay. Any other suggestion is appreciated.
09-13-2011 06:08 PM
A long time ago using Spartan 2 (I think) I tried to use carry chains to create
a programmable delay. I seem to remember using the MUXCY with the input
signal routing into the MUXCY at each level and the mux select determining
how many levels the input passed through the chain. The problem I had
was that changing the tap made no difference in the delay. On inspecting
the design, I found that the carry chains route vertically and flow up from
the bottom (as viewed in the FPGA editor). My input signal route also
came in from the bottom and routed up to each element in the chain. It
turns out that the routing delays almost exacly matched the carry chain
delays. Bottom line is that you need to hand route this sort of element
because routing delays are generally larger than logic delays regardless of the