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Visitor wvancura
Visitor
41,231 Views
Registered: ‎07-10-2008

Initializing a two dimentional array in verilog

I want to create a two dimensional array and initialize it when it is defined.

For eample:

 reg [15:0]  xyz_array[9:0];         <= How do I preset this to a known set of values? 

 reg [15:0]  abc = 16'h1234;     <= this is easy

 

I want to preset the values without having the program set them through a routine. The same as one would initialize a single dimensonal variable. currently I  initialized them as follows: 

 

if(RST) begin

xyz_array[9] <= 16'h1234

xyz_array[8] <= 16'h4321

...

xyz_array[0] <= 16h5467

end

Thanks

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4 Replies
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Advisor evgenis1
Advisor
41,223 Views
Registered: ‎12-03-2007

Re: Initializing a two dimentional array in verilog

Hi,

 

Section 3.10.3 (Memories) of the Verilog 2001 spec reads:

 

"An n-bit reg can be assigned a value in a single assignment, but a complete memory cannot. To assign avalue to a memory word, an index shall be specified..."

 

 

Thanks,

Evgeni 

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Instructor
Instructor
41,209 Views
Registered: ‎08-14-2007

Re: Initializing a two dimentional array in verilog

In the same module where the array is declared you should use an initial block to

set the config values for the array like:

 

initial begin

xyz_array[9] = 16'h1234

xyz_array[8] = 16'h4321

...

xyz_array[0] = 16h5467

end

It is also possible to initialize the array from an external file like:

 

initial $readmemh ("xyz_init_vals.hex",xyz_array);

 

where the file xyz_init_vals.hex contains:

 

1234

4321

. . .

5467

 

Note that the Verilog LRM allows addresses and comments, as well as more than one

value per line in the hex input file, however I have found that XST is much more restrictive.

Also the file should contain exactly the number of values as there are elements in the array.

 

HTH,

Gabor

-- Gabor
Visitor warlockoj
Visitor
36,476 Views
Registered: ‎01-21-2013

Re: Initializing a two dimentional array in verilog

Hi Gabor

 

I am trying to initialize a two dimentional array from text file containing one hex

data per line. I would synthesize the ROM with the initialized data which is basically

image data (in hex). It goes something like this:

 

parameter pix_max = 921600;

 

reg [7:0] img_rom[pix_max:0];

 

initial

     $readmemh("hex.txt", img_rom);

 

As it should, when I synthesize the RTL it works perfect with small images, that is upto pix_max = ~4900.

Problem is when I try to synthesize larger images, the synthesis process seems to never end.

 

Rig comprises  Intel Core i3 - 2100 @ 3.10 GHz and 4 GB DDR 3 RAM. OS - 32 bit windows 7 Ultimate.

FPGA - Spartan 3E 500k gates. Perhaps, it is the FPGA capacity mismatch?

 

Do you think it would be wise to consider using an external RAM to staore the image data and implement

RAM controller on the FPGA to transrecieve the image pixels. What is you best opinion?

 

AJ

 

 

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36,090 Views
Registered: ‎07-20-2013

Re: Initializing a two dimentional array in verilog

hi,

            have u explain me how to read data from external file or from RAM, 

                   i used to run the following code but it does not take the valu from external file

  

     

module ipp(out,clk);
output [7:0]out;
input clk;

parameter pix_max = 16383;

reg [7:0] img_rom[pix_max:0];

initial
$readmemh("hex.txt", img_rom,0,16383);

assign out = img_rom[10];
endmodule

 help me

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