04-16-2013 08:51 AM
Is anyone aware of a standard architecture or IP for communicating among FPGAs in a grid topology? I'm currently looking at deploying a grid of Artix-7 devices among multiple boards, with high-speed LVDS buses forwarding information from one FPGA, to the next.
I'd like to use some custom logic to automatically detect whether a packet is meant for the current FPGA, or if it needs to be forwarded to the next. I'd also like to use SERDES in the I/O pins to get high bandwidth (and maintain low latency). Since I don't have GTXs on the small Artix device, I need to forward a clock so I probably also need to use the local clocking resources of the tiles. Pushing the speed might require some fine-tuning of IODELAYs and BITSLIP circuitry in the I/Os.
I'm sure all of this is technically feasible, but the level of effort is a little daunting considering my project schedule.
Is there any particular Xilinx IP I should be leveraging to get this done efficiently? I'd love to be able to start with at least an LVDS bus architecture that takes care of all of the low-level clocking, delays, bitslipping, channel bonding, etc. It would save me a lot of time if I could start designing my custom logic at more of a link layer than the PHY layer.
Some of my initial research:
Aurora seems to be designed for GTX.
PCI is far too complicated for my point-to-point requirement.
Thanks for your help.
04-16-2013 09:04 AM
Before they spun off, and created a commerical product, this was the technology they used in their systems....
You might look at what they did that is in the public domain.
04-16-2013 11:31 AM
Thanks, Austin. I couldn't find too many details about previously developed IP. It appears as though those interfaces are more of a BYO-application-specific-core.
I did find this: http://www.archescomputing.com/lvds, which looks like it might be applicable.