UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Newbie kofri
Newbie
6,453 Views
Registered: ‎08-11-2011

Interconnect fpga pins

I hope it is not too stupid a question but I did not find anything about it: Is it possible to connect more than one fpga output pin to the same signal, so as to gain more driving strength? I guess the biggest problem would be timing?

 

Thanks for any help.

kofri

0 Kudos
6 Replies
Teacher rcingham
Teacher
6,446 Views
Registered: ‎09-09-2010

Re: Interconnect fpga pins

Possible, but not recommended. Use an external driver IC.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
0 Kudos
Scholar austin
Scholar
6,445 Views
Registered: ‎02-27-2008

Re: Interconnect fpga pins

k,

Possible, and people do it, often.

The concern is noted (timing) so one should constraint the paths, and the timing to be within +/- 100ps, or just use adjacent IO pins from IOB DFF clocked on the same clock resource. (which meets the timing specified above)

(It is very reasonable to do, and I have no idea why one would say it is "not recommended.")
Austin Lesea
Principal Engineer
Xilinx San Jose
0 Kudos
Instructor
Instructor
6,444 Views
Registered: ‎08-14-2007

Re: Interconnect fpga pins

It is possible to parallel outputs to increase drive, but you need to be careful not to

allow "fights" on the outputs.  If you need to drive in only one direction (e.g. open-drain)

then this is not an issue.  A typical example of this would be LED drivers.  Normally it

is not a good idea to parallel more than two outputs, as the load requiring the extra current

is also likely to be one that can cause damage to the FPGA.  External drivers are generally

cheaper and easier to replace.  Another suggestion is if you need assymmetric drive,

for example more low drive than high drive, you can parallel one active (totem-pole)

output with additional open drain outputs.  When paralleling active outputs you need

to push registers into the IOB's to ensure minimal skew between outputs that might

cause driver overlap.

 

-- Gabor

-- Gabor
0 Kudos
Advisor eilert
Advisor
6,433 Views
Registered: ‎08-14-2007

Re: Interconnect fpga pins

Hi Kofri,

just one more thing to keep in mind.

The I/Os of Xilinx FPGA are grouped into banks.

These have individual power connections.

The current that can be drawn via these power connections is quite limited.

So, if you intend to use multiple FPGA I/Os at their maximum load limit,

make sure the total current is below the limit of the I/O banks power supply pins.

 

Have a nice synthesis

  Eilert

0 Kudos
Highlighted
Newbie anny11
Newbie
6,429 Views
Registered: ‎08-12-2011

Re: Interconnect fpga pins

I am impressed by the quality of information on this forum. There are a lot of good resources here. I am sure I will visit this place again soon.

Tags (2)
0 Kudos
Newbie kofri
Newbie
6,397 Views
Registered: ‎08-11-2011

Re: Interconnect fpga pins

Thanks very much for the information!!

 

kofri

0 Kudos