08-11-2011 06:32 AM
I hope it is not too stupid a question but I did not find anything about it: Is it possible to connect more than one fpga output pin to the same signal, so as to gain more driving strength? I guess the biggest problem would be timing?
Thanks for any help.
08-11-2011 07:33 AM
08-11-2011 07:46 AM
08-11-2011 07:52 AM
It is possible to parallel outputs to increase drive, but you need to be careful not to
allow "fights" on the outputs. If you need to drive in only one direction (e.g. open-drain)
then this is not an issue. A typical example of this would be LED drivers. Normally it
is not a good idea to parallel more than two outputs, as the load requiring the extra current
is also likely to be one that can cause damage to the FPGA. External drivers are generally
cheaper and easier to replace. Another suggestion is if you need assymmetric drive,
for example more low drive than high drive, you can parallel one active (totem-pole)
output with additional open drain outputs. When paralleling active outputs you need
to push registers into the IOB's to ensure minimal skew between outputs that might
cause driver overlap.
08-11-2011 11:23 PM
just one more thing to keep in mind.
The I/Os of Xilinx FPGA are grouped into banks.
These have individual power connections.
The current that can be drawn via these power connections is quite limited.
So, if you intend to use multiple FPGA I/Os at their maximum load limit,
make sure the total current is below the limit of the I/O banks power supply pins.
Have a nice synthesis
08-12-2011 12:41 AM