Interfacing asynchronous bus with CPLD: to latch or not to latch

[doragasu]

I'm new to programmable logic and VHDL, and want to make an interface to a Z80 bus using a CPLD (XC9500XL family).  You can see several bus captures for reference at the end of this web page. The interface must handle bankswitching (e.g. it must have some internal registers that the CPU can set to handle the upper lines of the system RAM/ROM).

Unfortunately, as the bus is asynchronous, and I have no clock signal, my first attemp implements the registers using latches. I know using latches is discouraged (specially when they appear because poor coding: this is not the case, they are there on purpose), but as memory accesses are relatively slow (1 MHz), could this approach work? How do latch implementations in Xilinx CPLDs behave?

I have been recommended elsewhere using a higher clock for the CPLD (e.g. 4 MHz) to sample the asynchronous bus, avoiding latches, but I'm not sure if this is necessary, and I suspect it might introduce additional complexity and problems (e.g. metastability due to the clock being out of sync).

Another option I'm considering is a variant of the oversampling approach above, using a PLL driven by the 1 MHz system clock, instead of a 4 MHz clock generator. This way, the clock used for sampling should always be in sync with the Z80 clock. But I would like to avoid this approach if possible because after a thorough search, PLL chips capable of operating at 1MHz input, are expensive (most of them need an input clock greater than 10 MHz).

Any suggestions for this PLD noob would be greatly appreciated!

[gszakacs · Accepted solution]

9500XL is not good with latches.  Its registers are normally edge-triggered, but can build latches using their asynchronous set and reset inputs.  This adds additional logic complexity (product term usage).  If you picked the 9500XL because of its 5V tolerance, your next best bet would be a small Spartan II FPGA, which is also 5V tolerant and has registers that can be configured as transparent latches.  Otherwise you would be better off adding level translators and using any newer logic family including CoolRunner II, whose registers can also be configured as transparent latches.  However none of these newer families are 5V tolerant.

The idea to oversample with a clock is actually good for a system this slow, and that is typically how this sort of interface is handled in an FPGA.  Going to an even higher frequency than 4 MHz would allow you to have plenty of stages to mitigate any metastability issues.  Basically each of the asynchronous bus signals are sampled with a short shift register and only the 2nd and subsequent shift stages used by the design.  At a high enough frequency the shift register's delay does not eat up the available cycle time to respond with output from the CPLD.  Remember that clock to output times on a CPLD are a tiny fraction of the clock to output delay of a 1970's era microprocessor like the Z80.

[doragasu]

Thanks a lot for the fast and detailed answer!

So if I understood correctly, latches should not be a problem if I use a CoolRunnerII CPLD, right? 5V are not a problem since I was going to use level shifters anyway (because I also want to use some 3.3V only memory chips). I didn't consider a CoolRunnerII device before, because I wanted to avoid generating 1.8V, but that's for sure something I can live with.

[gszakacs]

Check out the Coolrunner 2 family data sheet page 5 for a description of the macrocell.  It is much more flexible than the XC9500XL series macrocell.  You can have transparent latches, standard D or T flip-flop, or "dual edge" flip-flops which effectively double the clock frequency.  If you have some code already written, you can try to build in in an ISE project selecting the CR2 "automatic" part selection allowing the fitter to find the smallest Coolrunner 2 part that fits your design.

Also note that these parts are very low power so you could easily use a linear regulator to make 1.8V from 3.3v without dissipating too much heat in the regulator.

[doragasu]

Tried changing the design settings to use a Coolrunner 2 part. XST still warns about latches being generated. The latches are exactly the ones I expected, so I suppose I can safely ignore them, right?

Now the automatically generated (using "Lock Pins") LOC constraints make a lot more sense and are a lot easier to route in the PCB than the previously generated for the XC9500XL CPLD.

Again, thanks for your suggestions!

[gszakacs]

Yes, you can ignore the latch warnings.  On the rare occasions when I code latches intentionally, I usually make the signal name contain "latch" so it's clear that it was my intent.  That way I don't skim over the warning if I create a latch unintentionally.