Is there any xilinx ip or module that can accomplish clock recovery?
Dear Xilinx support team,
I am looking for a module or maybe a design idea that can help me achieve clock recovery in my design.
The design has a master board and a slave board, the master is providing clock and data. The slave is using the clock and the data from the master.
The challenge is that how to make slave board recover from a short period of time lacking master clock, and still reading data, though the data needs to be flushed if it's read from the time when clock is missing.
I know using digital phase lock loop (DPLL) can help with the case. Is there a simpler way than using DPLL to accomplish this? Or is there a module or ip that i can use that already does the DPLL for me. I know implement DPLL is complicate and may not be necessary because the system I am working with does have a clock line so no need to derive clock from the data.