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Anonymous
Not applicable
3,800 Views

Is this procedure(code) is synthesizable?

Hi,

      I have doubt in synthesizing as well as i am getting error when i synthesizing.According to my knowledge WAIT statement is not synthesizable.Wether EXIT statement is synthesizable?

---------------------------------------------------------------------------------------------------------------

procedure read_out_x
            (signal CSB,sck : in std_logic;
            signal so_reg,so_on1 : out std_logic
            ) is
begin
report " Readx loop entered ";
so_on1 <='0';
read_loopx : loop
    wait until (SCK'EVENT and SCK ='0') or (CSB'EVENT and CSB='1');
    exit read_loopx when (CSB='1' ) ;
        wait for Tv;
        SO_reg <= 'X';
              so_on1 <= '1';
end loop;
        SO_reg <= '0';
         so_on1 <= '0';    

 report " Readx loop exited";
end read_out_x;

 

---------------------------------------------------------------------------------------------------------------------------------

                                                Above WAIT statement is in the code.So i am removing that WAIT statement and writing like as below.I am getting Error as

##Edge or event as condition for a return, exit or next statement is not supported

If i comment EXIT Statement am getting error as

## statement is not synthesizable since it does not holds it's value under NOT(clock_edge) condition.

 

*******************************************************************************************************

procedure read_out_x
            (signal CSB,sck : in std_logic;
            signal so_reg,so_on1 : out std_logic
            ) is
begin
report " Readx loop entered ";
so_on1 <='0';
read_loopx : loop
    if(SCK'EVENT and SCK ='0') then
      if(CSB'EVENT and CSB = '1') then
       if(Tv_delay_cnt = '1') then
    --    wait for Tv;
        SO_reg <= 'X';
              so_on1 <= '1';
         exit read_loopx when (CSB='1') ;
           else
               Tv_delay_cnt    := not Tv_delay;
           end if;
          end if;
         end if;     
end loop;
   
        SO_reg <= '0';
         so_on1 <= '0';    

 report " Readx loop exited";
end read_out_x;

 

*******************************************************************************************************

 

                                 Please tell me How to synthesize this code by removing this error.

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3 Replies
rcingham
Teacher
Teacher
3,796 Views
Registered: ‎09-09-2010

Without doing your work for you, I would suggest that first you write the task as a process. Then, when you have something that works properly and synthesizes, convert it - or most of it - to a procedure.

------------------------------------------
"If it don't work in simulation, it won't work on the board."
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gszakacs
Professor
Professor
3,792 Views
Registered: ‎08-14-2007

Just another clarification on loops for synthesis:

 

1)  All loops get "unrolled" so you have the potential to create a very large

amount of logic even if the loop is synthesizable.

 

2) Synthesizable loops may not have any event conditions in them.  You can

have a wait for 2 ns (time - not event) but it will be ignored.  So in any case

the entire loop unrolls to something combinatorial.

 

3) The loop must always have the same number of iterations, and the number of

iterations must be known at the time of synthesis.  This means you can't initialize

the loop variable with a signal for example, and it also means you can't use EXIT.

However you can use conditional statements inside a loop.  This means that the

loop can effectively have a variable number of iterations if you use conditions to

enable the effects of each iteration.  So for example rather than EXIT on a particular

condition, you can set a variable on that condition, then use if (that variable = '1')

to enable each loops effects.

 

HTH,

Gabor

-- Gabor
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eilert
Teacher
Teacher
3,783 Views
Registered: ‎08-14-2007

Hi Mahesh,

you already got some valuable informations from rcingham and Gabor, but let me add this.

There exists a standard (IEEE1076-yyyy part 4, where yyyy is the year of release) that descibes what language constructs can be used for synthesis.

It explains in detail the different ways synchronous constructs can be written.

 

In your case it's even simpler to explain.

- Wait for isn't synthesizable.

- Wait until (clk'event and clk = '0');  is synthesizable under certain circumstances when you follow the rules of the standard.

 

A synchronous construct basically creates some (D-)Flipflop or Register.

Now your code has two Clock dependencies (SCK and CSB), and a synthesis tool will/must not do clock gating.

(You can gate the clocks manually, but that will cause trouble too.)

So since your FF can not be driven by two clocks at the same time, this construct will be rejected.

 

Have a nice synthesis

  Eilert

 

 

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